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Searched refs:Op0VT (Results 1 – 17 of 17) sorted by relevance

/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2124 EVT Op0VT = Op0.getValueType(); in LowerOperation() local
2129 if (Op0VT.isFixedLengthVector()) in LowerOperation()
2134 if (!Op0VT.isVector()) { in LowerOperation()
2135 auto BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1); in LowerOperation()
2145 if (!VT.isVector() && Op0VT.isFixedLengthVector()) { in LowerOperation()
2151 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
2156 if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
5085 EVT Op0VT = Op0.getValueType(); in ReplaceNodeResults() local
5087 if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) { in ReplaceNodeResults()
5095 } else if (!VT.isVector() && Op0VT.isFixedLengthVector() && in ReplaceNodeResults()
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2124 EVT Op0VT = Op0.getValueType(); in LowerOperation() local
2129 if (Op0VT.isFixedLengthVector()) in LowerOperation()
2134 if (!Op0VT.isVector()) { in LowerOperation()
2135 auto BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1); in LowerOperation()
2145 if (!VT.isVector() && Op0VT.isFixedLengthVector()) { in LowerOperation()
2151 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
2156 if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
5085 EVT Op0VT = Op0.getValueType(); in ReplaceNodeResults() local
5087 if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) { in ReplaceNodeResults()
5095 } else if (!VT.isVector() && Op0VT.isFixedLengthVector() && in ReplaceNodeResults()
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2124 EVT Op0VT = Op0.getValueType(); in LowerOperation() local
2129 if (Op0VT.isFixedLengthVector()) in LowerOperation()
2134 if (!Op0VT.isVector()) { in LowerOperation()
2135 auto BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1); in LowerOperation()
2145 if (!VT.isVector() && Op0VT.isFixedLengthVector()) { in LowerOperation()
2151 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
2156 if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
5085 EVT Op0VT = Op0.getValueType(); in ReplaceNodeResults() local
5087 if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) { in ReplaceNodeResults()
5095 } else if (!VT.isVector() && Op0VT.isFixedLengthVector() && in ReplaceNodeResults()
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2124 EVT Op0VT = Op0.getValueType(); in LowerOperation() local
2129 if (Op0VT.isFixedLengthVector()) in LowerOperation()
2134 if (!Op0VT.isVector()) { in LowerOperation()
2135 auto BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1); in LowerOperation()
2145 if (!VT.isVector() && Op0VT.isFixedLengthVector()) { in LowerOperation()
2151 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
2156 if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
5085 EVT Op0VT = Op0.getValueType(); in ReplaceNodeResults() local
5087 if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) { in ReplaceNodeResults()
5095 } else if (!VT.isVector() && Op0VT.isFixedLengthVector() && in ReplaceNodeResults()
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2124 EVT Op0VT = Op0.getValueType(); in LowerOperation() local
2129 if (Op0VT.isFixedLengthVector()) in LowerOperation()
2134 if (!Op0VT.isVector()) { in LowerOperation()
2135 auto BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1); in LowerOperation()
2145 if (!VT.isVector() && Op0VT.isFixedLengthVector()) { in LowerOperation()
2151 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
2156 if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
5085 EVT Op0VT = Op0.getValueType(); in ReplaceNodeResults() local
5087 if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) { in ReplaceNodeResults()
5095 } else if (!VT.isVector() && Op0VT.isFixedLengthVector() && in ReplaceNodeResults()
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2376 EVT Op0VT = Op0.getValueType(); in LowerOperation() local
2381 if (Op0VT.isFixedLengthVector()) in LowerOperation()
2386 if (!Op0VT.isVector()) { in LowerOperation()
2387 auto BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1); in LowerOperation()
2397 if (!VT.isVector() && Op0VT.isFixedLengthVector()) { in LowerOperation()
2403 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
2408 if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
5669 EVT Op0VT = Op0.getValueType(); in ReplaceNodeResults() local
5671 if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) { in ReplaceNodeResults()
5679 } else if (!VT.isVector() && Op0VT.isFixedLengthVector() && in ReplaceNodeResults()
[all …]
/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp2037 EVT Op0VT = N0.getOperand(0).getValueType(); in SimplifyBinOpWithSameOpcodeHands() local
2042 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || in SimplifyBinOpWithSameOpcodeHands()
2044 (!TLI.isZExtFree(VT, Op0VT) || in SimplifyBinOpWithSameOpcodeHands()
2045 !TLI.isTruncateFree(Op0VT, VT)) && in SimplifyBinOpWithSameOpcodeHands()
2046 TLI.isTypeLegal(Op0VT))) && in SimplifyBinOpWithSameOpcodeHands()
2048 Op0VT == N1.getOperand(0).getValueType() && in SimplifyBinOpWithSameOpcodeHands()
2049 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { in SimplifyBinOpWithSameOpcodeHands()
/dports/devel/llvm70/llvm-7.0.1.src/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp3686 EVT Op0VT = N0.getOperand(0).getValueType(); in SimplifyBinOpWithSameOpcodeHands() local
3692 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || in SimplifyBinOpWithSameOpcodeHands()
3694 (!TLI.isZExtFree(VT, Op0VT) || in SimplifyBinOpWithSameOpcodeHands()
3695 !TLI.isTruncateFree(Op0VT, VT)) && in SimplifyBinOpWithSameOpcodeHands()
3696 TLI.isTypeLegal(Op0VT))) && in SimplifyBinOpWithSameOpcodeHands()
3698 Op0VT == N1.getOperand(0).getValueType() && in SimplifyBinOpWithSameOpcodeHands()
3699 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { in SimplifyBinOpWithSameOpcodeHands()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12380 EVT Op0VT = A.getOperand(0).getValueType(); in performVecReduceAddCombine() local
12381 if (Op0VT != MVT::v8i8 && Op0VT != MVT::v16i8) in performVecReduceAddCombine()
12388 B = DAG.getConstant(1, DL, Op0VT); in performVecReduceAddCombine()
12393 DAG.getConstant(0, DL, Op0VT == MVT::v8i8 ? MVT::v2i32 : MVT::v4i32); in performVecReduceAddCombine()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12380 EVT Op0VT = A.getOperand(0).getValueType(); in performVecReduceAddCombine() local
12381 if (Op0VT != MVT::v8i8 && Op0VT != MVT::v16i8) in performVecReduceAddCombine()
12388 B = DAG.getConstant(1, DL, Op0VT); in performVecReduceAddCombine()
12393 DAG.getConstant(0, DL, Op0VT == MVT::v8i8 ? MVT::v2i32 : MVT::v4i32); in performVecReduceAddCombine()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12380 EVT Op0VT = A.getOperand(0).getValueType(); in performVecReduceAddCombine() local
12381 if (Op0VT != MVT::v8i8 && Op0VT != MVT::v16i8) in performVecReduceAddCombine()
12388 B = DAG.getConstant(1, DL, Op0VT); in performVecReduceAddCombine()
12393 DAG.getConstant(0, DL, Op0VT == MVT::v8i8 ? MVT::v2i32 : MVT::v4i32); in performVecReduceAddCombine()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12634 EVT Op0VT = A.getOperand(0).getValueType(); in performVecReduceAddCombine() local
12635 if (Op0VT != MVT::v8i8 && Op0VT != MVT::v16i8) in performVecReduceAddCombine()
12642 B = DAG.getConstant(1, DL, Op0VT); in performVecReduceAddCombine()
12647 DAG.getConstant(0, DL, Op0VT == MVT::v8i8 ? MVT::v2i32 : MVT::v4i32); in performVecReduceAddCombine()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12380 EVT Op0VT = A.getOperand(0).getValueType(); in performVecReduceAddCombine() local
12381 if (Op0VT != MVT::v8i8 && Op0VT != MVT::v16i8) in performVecReduceAddCombine()
12388 B = DAG.getConstant(1, DL, Op0VT); in performVecReduceAddCombine()
12393 DAG.getConstant(0, DL, Op0VT == MVT::v8i8 ? MVT::v2i32 : MVT::v4i32); in performVecReduceAddCombine()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12380 EVT Op0VT = A.getOperand(0).getValueType(); in performVecReduceAddCombine() local
12381 if (Op0VT != MVT::v8i8 && Op0VT != MVT::v16i8) in performVecReduceAddCombine()
12388 B = DAG.getConstant(1, DL, Op0VT); in performVecReduceAddCombine()
12393 DAG.getConstant(0, DL, Op0VT == MVT::v8i8 ? MVT::v2i32 : MVT::v4i32); in performVecReduceAddCombine()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11249 EVT Op0VT = Op0.getOperand(0).getValueType(); in performVecReduceAddCombine() local
11250 if (Op0VT != MVT::v16i8) in performVecReduceAddCombine()
11254 SDValue Ones = DAG.getConstant(1, DL, Op0VT); in performVecReduceAddCombine()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11673 EVT Op0VT = Op0.getOperand(0).getValueType(); in performVecReduceAddCombine() local
11674 if (Op0VT != MVT::v16i8) in performVecReduceAddCombine()
11678 SDValue Ones = DAG.getConstant(1, DL, Op0VT); in performVecReduceAddCombine()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11673 EVT Op0VT = Op0.getOperand(0).getValueType(); in performVecReduceAddCombine() local
11674 if (Op0VT != MVT::v16i8) in performVecReduceAddCombine()
11678 SDValue Ones = DAG.getConstant(1, DL, Op0VT); in performVecReduceAddCombine()