1 #ifndef __XSCOM_P10_REGS_H__ 2 #define __XSCOM_P10_REGS_H__ 3 4 /* Core FIR (Fault Isolation Register) */ 5 #define P10_CORE_FIR 0x440 6 7 #define P10_CORE_FIRMASK_OR 0x445 8 9 /* Core WOF (Whose On First) */ 10 #define P10_CORE_WOF 0x448 11 12 #define P10_MALFUNC_ALERT 0x00090022 13 14 #define P10_NX_STATUS_REG 0x02011040 /* NX status register */ 15 #define P10_NX_DMA_ENGINE_FIR 0x02011100 /* DMA & Engine FIR Data Register */ 16 #define P10_NX_PBI_FIR 0x02011080 /* PowerBus Interface FIR Register */ 17 18 #define P10_EC_CORE_THREAD_STATE 0x412 /* XXX P10 is this right? */ 19 #define P10_THREAD_STOPPED(t) PPC_BIT(56 + (t)) 20 21 #define P10_EC_THREAD_INFO 0x413 22 #define P10_THREAD_ACTIVE(t) PPC_BIT(t) 23 24 #define P10_EC_RAS_STATUS 0x454 25 #define P10_THREAD_MAINT(t) PPC_BIT(0 + 8*(t)) 26 #define P10_THREAD_QUIESCED(t) PPC_BIT(1 + 8*(t)) 27 #define P10_THREAD_ICT_EMPTY(t) PPC_BIT(2 + 8*(t)) 28 29 #define P10_EC_DIRECT_CONTROLS 0x449 30 #define P10_THREAD_STOP(t) PPC_BIT(7 + 8*(t)) 31 #define P10_THREAD_START(t) PPC_BIT(6 + 8*(t)) 32 #define P10_THREAD_SRESET(t) PPC_BIT(4 + 8*(t)) 33 #define P10_THREAD_CLEAR_MAINT(t) PPC_BIT(3 + 8*(t)) 34 #define P10_THREAD_PWR(t) PPC_BIT(32 + 8*(t)) 35 36 #define P10_QME_FIR 0x000 37 38 #define P10_QME_SPWU_HYP 0x83c 39 #define P10_SPWU_REQ PPC_BIT(0) 40 #define P10_SPWU_DONE PPC_BIT(4) 41 42 #define P10_QME_SSH_HYP 0x82c 43 #define P10_SSH_CORE_GATED PPC_BIT(0) 44 #define P10_SSH_SPWU_DONE PPC_BIT(1) 45 46 #define P10_NCU_STATUS_REG 0x64f 47 #define P10_NCU_SPEC_BAR 0x650 48 #define P10_NCU_SPEC_BAR_ENABLE PPC_BIT(0) 49 #define P10_NCU_SPEC_BAR_256K PPC_BIT(1) 50 #define P10_NCU_SPEC_BAR_ADDRMSK 0x000fffffffffc000ull /* 16k aligned */ 51 52 #define P10_NCU_DARN_BAR 0x651 53 #define P10_NCU_DARN_BAR_EN PPC_BIT(0) 54 #define P10_NCU_DARN_BAR_ADDRMSK 0x000ffffffffff000ull /* 4k aligned */ 55 56 #endif /* __XSCOM_P10_REGS_H__ */ 57