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Searched refs:PENDING_REG (Results 1 – 25 of 57) sorted by relevance

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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
/dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) macro
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
110 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()

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