Home
last modified time | relevance | path

Searched refs:PG0 (Results 1 – 25 of 1566) sorted by relevance

12345678910>>...63

/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dsve-fixed-length-masked-gather.ll32 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
54 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
187 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
194 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl2
330 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
477 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
493 ; CHECK: ptrue [[PG0:p[0-9]+]].d, vl4
583 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
713 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
835 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
[all …]
H A Dsve-fixed-length-masked-scatter.ll32 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
175 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
306 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
340 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].s, vl8
443 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
457 ; CHECK: ptrue [[PG0:p[0-9]+]].d, vl4
472 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
537 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
657 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
768 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
[all …]
H A Dsve-fixed-length-masked-loads.ll30 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].h, vl4
59 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl2
75 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl4
94 ; CHECK-NEXT: st1w { [[Z0]].s }, [[PG0]], [x8]
154 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].b, vl64
170 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].h, vl32
186 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].s, vl16
202 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
218 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
235 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
[all …]
H A Dsve-fixed-length-masked-stores.ll90 ; CHECK: ptrue [[PG0:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
91 ; CHECK-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
92 ; CHECK-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
93 ; CHECK-NEXT: fcmeq [[PG1:p[0-9]+]].s, [[PG0]]/z, [[Z0]].s, [[Z1]].s
106 ; VBITS_GE_512-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
107 ; VBITS_GE_512-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
108 ; VBITS_GE_512-NEXT: fcmeq [[PG1:p[0-9]+]].s, [[PG0]]/z, [[Z0]].s, [[Z1]].s
121 ; VBITS_GE_1024-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
122 ; VBITS_GE_1024-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
136 ; VBITS_GE_2048-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/
H A Dsve-fixed-length-masked-gather.ll32 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
54 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
187 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
194 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl2
330 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
477 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
493 ; CHECK: ptrue [[PG0:p[0-9]+]].d, vl4
583 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
713 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
835 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
[all …]
H A Dsve-fixed-length-masked-scatter.ll32 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
175 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
306 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
340 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].s, vl8
443 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
457 ; CHECK: ptrue [[PG0:p[0-9]+]].d, vl4
472 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
537 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
657 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
768 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
[all …]
H A Dsve-fixed-length-masked-loads.ll30 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].h, vl4
59 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl2
75 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl4
94 ; CHECK-NEXT: st1w { [[Z0]].s }, [[PG0]], [x8]
154 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].b, vl64
170 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].h, vl32
186 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].s, vl16
202 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
218 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
235 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
[all …]
H A Dsve-fixed-length-masked-stores.ll90 ; CHECK: ptrue [[PG0:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
91 ; CHECK-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
92 ; CHECK-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
93 ; CHECK-NEXT: fcmeq [[PG1:p[0-9]+]].s, [[PG0]]/z, [[Z0]].s, [[Z1]].s
106 ; VBITS_GE_512-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
107 ; VBITS_GE_512-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
108 ; VBITS_GE_512-NEXT: fcmeq [[PG1:p[0-9]+]].s, [[PG0]]/z, [[Z0]].s, [[Z1]].s
121 ; VBITS_GE_1024-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
122 ; VBITS_GE_1024-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
136 ; VBITS_GE_2048-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dsve-fixed-length-masked-gather.ll32 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
54 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
187 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
194 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl2
330 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
477 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
493 ; CHECK: ptrue [[PG0:p[0-9]+]].d, vl4
583 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
713 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
835 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
[all …]
H A Dsve-fixed-length-masked-scatter.ll32 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
175 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
306 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
340 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].s, vl8
443 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
457 ; CHECK: ptrue [[PG0:p[0-9]+]].d, vl4
472 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
537 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
657 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
768 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
[all …]
H A Dsve-fixed-length-masked-loads.ll30 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].h, vl4
59 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl2
75 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl4
94 ; CHECK-NEXT: st1w { [[Z0]].s }, [[PG0]], [x8]
154 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].b, vl64
170 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].h, vl32
186 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].s, vl16
202 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
218 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
235 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
[all …]
H A Dsve-fixed-length-masked-stores.ll90 ; CHECK: ptrue [[PG0:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
91 ; CHECK-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
92 ; CHECK-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
93 ; CHECK-NEXT: fcmeq [[PG1:p[0-9]+]].s, [[PG0]]/z, [[Z0]].s, [[Z1]].s
106 ; VBITS_GE_512-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
107 ; VBITS_GE_512-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
108 ; VBITS_GE_512-NEXT: fcmeq [[PG1:p[0-9]+]].s, [[PG0]]/z, [[Z0]].s, [[Z1]].s
121 ; VBITS_GE_1024-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
122 ; VBITS_GE_1024-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
136 ; VBITS_GE_2048-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dsve-fixed-length-masked-gather.ll32 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
54 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
187 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
194 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl2
330 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
477 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
493 ; CHECK: ptrue [[PG0:p[0-9]+]].d, vl4
583 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
713 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
835 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
[all …]
H A Dsve-fixed-length-masked-scatter.ll32 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
175 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
306 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
340 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].s, vl8
443 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
457 ; CHECK: ptrue [[PG0:p[0-9]+]].d, vl4
472 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
537 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl4
657 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
768 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].d, vl2
[all …]
H A Dsve-fixed-length-masked-loads.ll30 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].h, vl4
59 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl2
75 ; CHECK-NEXT: ptrue [[PG0:p[0-9]+]].s, vl4
94 ; CHECK-NEXT: st1w { [[Z0]].s }, [[PG0]], [x8]
154 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].b, vl64
170 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].h, vl32
186 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].s, vl16
202 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
218 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
235 ; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
[all …]
H A Dsve-fixed-length-masked-stores.ll90 ; CHECK: ptrue [[PG0:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
91 ; CHECK-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
92 ; CHECK-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
93 ; CHECK-NEXT: fcmeq [[PG1:p[0-9]+]].s, [[PG0]]/z, [[Z0]].s, [[Z1]].s
106 ; VBITS_GE_512-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
107 ; VBITS_GE_512-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
108 ; VBITS_GE_512-NEXT: fcmeq [[PG1:p[0-9]+]].s, [[PG0]]/z, [[Z0]].s, [[Z1]].s
121 ; VBITS_GE_1024-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
122 ; VBITS_GE_1024-NEXT: ld1w { [[Z1:z[0-9]+]].s }, [[PG0]]/z, [x1]
136 ; VBITS_GE_2048-NEXT: ld1w { [[Z0:z[0-9]+]].s }, [[PG0]]/z, [x0]
[all …]
/dports/lang/micropython/micropython-1.17/ports/stm32/boards/STM32L476DISC/
H A Dpins.csv97 PG0,PG0
/dports/lang/micropython/micropython-1.17/ports/stm32/boards/LIMIFROG/
H A Dpins.csv97 PG0,PG0
/dports/lang/micropython/micropython-1.17/ports/stm32/boards/NUCLEO_F413ZH/
H A Dpins.csv97 PG0,PG0
/dports/lang/micropython/micropython-1.17/ports/stm32/boards/STM32F429DISC/
H A Dpins.csv87 PG0,PG0
/dports/lang/micropython/micropython-1.17/ports/stm32/boards/NUCLEO_F412ZG/
H A Dpins.csv97 PG0,PG0
/dports/devel/urjtag/urjtag-2021.03/data/analog/bf592/
H A Dbf59229 signal PG0
81 bit 12 I ? PG0
82 bit 13 O ? PG0 14 0 Z
/dports/lang/micropython/micropython-1.17/ports/stm32/boards/NUCLEO_F429ZI/
H A Dpins.csv87 PG0,PG0
/dports/devel/tinygo/tinygo-0.14.1/src/machine/
H A Dmachine_atmega2560.go70 PG0 = portG + 0 const
115 case p >= PG0 && p <= PG5:
/dports/devel/urjtag/urjtag-2021.03/data/analog/bf506/
H A Dbf50618 signal PG0
137 bit 66 O 1 PG0 67 0 Z
138 bit 65 I 1 PG0

12345678910>>...63