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Searched refs:PHY_TMR_LPCLK_CFG (Results 1 – 6 of 6) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_dsi_reg.h57 #define PHY_TMR_LPCLK_CFG 0x98 /* clock lane timing configuration */ macro
H A Ddw_drm_dsi.c353 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10), in dsi_set_phy_timer()
355 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10), in dsi_set_phy_timer()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_dsi_reg.h57 #define PHY_TMR_LPCLK_CFG 0x98 /* clock lane timing configuration */ macro
H A Ddw_drm_dsi.c353 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10), in dsi_set_phy_timer()
355 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10), in dsi_set_phy_timer()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_dsi_reg.h57 #define PHY_TMR_LPCLK_CFG 0x98 /* clock lane timing configuration */ macro
H A Ddw_drm_dsi.c353 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10), in dsi_set_phy_timer()
355 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10), in dsi_set_phy_timer()