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Searched refs:PLL2_CLOCK (Results 1 – 25 of 70) sorted by relevance

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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/mx51/
H A Dclock.c35 PLL2_CLOCK, enumerator
42 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
87 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in get_periph_clk()
152 freq = decode_pll(mxc_plls[PLL2_CLOCK], in get_uart_clk()
214 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], in imx_get_cspiclk()
278 freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in do_mx51_showclocks()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/mx51/
H A Dclock.c35 PLL2_CLOCK, enumerator
42 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
87 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in get_periph_clk()
152 freq = decode_pll(mxc_plls[PLL2_CLOCK], in get_uart_clk()
214 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], in imx_get_cspiclk()
278 freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in do_mx51_showclocks()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/mx51/
H A Dclock.c35 PLL2_CLOCK, enumerator
42 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
87 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in get_periph_clk()
152 freq = decode_pll(mxc_plls[PLL2_CLOCK], in get_uart_clk()
214 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], in imx_get_cspiclk()
278 freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in do_mx51_showclocks()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/mx51/
H A Dclock.c35 PLL2_CLOCK, enumerator
42 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
87 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in get_periph_clk()
152 freq = decode_pll(mxc_plls[PLL2_CLOCK], in get_uart_clk()
214 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], in imx_get_cspiclk()
278 freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in do_mx51_showclocks()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/mx51/
H A Dclock.c35 PLL2_CLOCK, enumerator
42 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
87 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in get_periph_clk()
152 freq = decode_pll(mxc_plls[PLL2_CLOCK], in get_uart_clk()
214 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], in imx_get_cspiclk()
278 freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in do_mx51_showclocks()
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/mx51/
H A Dclock.c35 PLL2_CLOCK, enumerator
42 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
87 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in get_periph_clk()
152 freq = decode_pll(mxc_plls[PLL2_CLOCK], in get_uart_clk()
214 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], in imx_get_cspiclk()
278 freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in do_mx51_showclocks()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/mx51/
H A Dclock.c35 PLL2_CLOCK, enumerator
42 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
87 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in get_periph_clk()
152 freq = decode_pll(mxc_plls[PLL2_CLOCK], in get_uart_clk()
214 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], in imx_get_cspiclk()
278 freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); in do_mx51_showclocks()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c20 PLL2_CLOCK, enumerator
30 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
270 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
331 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
662 case PLL2_CLOCK: in config_pll_clk()
952 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c20 PLL2_CLOCK, enumerator
30 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
270 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
331 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
662 case PLL2_CLOCK: in config_pll_clk()
952 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c22 PLL2_CLOCK, enumerator
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
664 case PLL2_CLOCK: in config_pll_clk()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()

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