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Searched refs:PLLM_OUT (Results 1 – 12 of 12) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/tegra/
H A Dclk-tegra20.c69 #define PLLM_OUT 0x94 macro
648 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
651 clk_base + PLLM_OUT, 1, 0, in tegra20_pll_init()
H A Dclk-tegra114.c95 #define PLLM_OUT 0x94 macro
935 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
938 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra114_pll_init()
H A Dclk-tegra30.c83 #define PLLM_OUT 0x94 macro
836 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
839 clk_base + PLLM_OUT, 1, 0, in tegra30_pll_init()
H A Dclk-tegra124.c44 #define PLLM_OUT 0x94 macro
1133 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra124_pll_init()
1136 clk_base + PLLM_OUT, 1, 0, in tegra124_pll_init()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/tegra/
H A Dclk-tegra20.c69 #define PLLM_OUT 0x94 macro
648 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
651 clk_base + PLLM_OUT, 1, 0, in tegra20_pll_init()
H A Dclk-tegra114.c95 #define PLLM_OUT 0x94 macro
935 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
938 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra114_pll_init()
H A Dclk-tegra30.c83 #define PLLM_OUT 0x94 macro
836 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
839 clk_base + PLLM_OUT, 1, 0, in tegra30_pll_init()
H A Dclk-tegra124.c44 #define PLLM_OUT 0x94 macro
1133 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra124_pll_init()
1136 clk_base + PLLM_OUT, 1, 0, in tegra124_pll_init()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/tegra/
H A Dclk-tegra20.c69 #define PLLM_OUT 0x94 macro
648 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
651 clk_base + PLLM_OUT, 1, 0, in tegra20_pll_init()
H A Dclk-tegra30.c83 #define PLLM_OUT 0x94 macro
836 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
839 clk_base + PLLM_OUT, 1, 0, in tegra30_pll_init()
H A Dclk-tegra114.c95 #define PLLM_OUT 0x94 macro
935 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
938 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra114_pll_init()
H A Dclk-tegra124.c44 #define PLLM_OUT 0x94 macro
1133 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra124_pll_init()
1136 clk_base + PLLM_OUT, 1, 0, in tegra124_pll_init()