/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 43 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 50 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 51 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 288 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 289 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 290 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 43 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 50 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 51 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 288 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 289 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 290 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 43 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 50 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 51 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 288 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 289 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 290 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 43 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 50 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 51 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 288 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 289 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 290 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/clk/rockchip/ |
H A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ macro 55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); 56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); 59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk() 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk() 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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