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/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Dppc-opc.c1907 #define POWER4 PPC_OPCODE_POWER4 macro
1973 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476, {0}},
3495 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
3496 {"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}},
3776 {"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
3777 {"dcbtst", X(31,246), X_MASK, PPC, POWER4, {CT, RA, RB}},
3804 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}},
3812 {"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
3813 {"dcbt", X(31,278), X_MASK, PPC, POWER4, {CT, RA, RB}},
4868 {"lq", OP(56), OP_MASK, POWER4, PPC476, {RTQ, DQ, RAQ}},
[all …]
/dports/math/math77/MATH77/
H A Ddrdval.f62 DOUBLE PRECISION LAMDA,LOLIM,MU,POWER4,SIGMA,S1,S2,UPLIM,XN,XNDEV local
127 POWER4 = 1.0d0
144 RD = 3.0d0 * SIGMA + POWER4 * (1.0d0+S1+S2) / (MU*SQRT(MU))
151 SIGMA = SIGMA + POWER4 / (ZNROOT * (ZN + LAMDA))
152 POWER4 = POWER4 * 0.25d0
H A Dsrdval.f62 REAL LAMDA,LOLIM,MU,POWER4,SIGMA,S1,S2,UPLIM,XN,XNDEV local
127 POWER4 = 1.0e0
144 RD = 3.0e0 * SIGMA + POWER4 * (1.0e0+S1+S2) / (MU*SQRT(MU))
151 SIGMA = SIGMA + POWER4 / (ZNROOT * (ZN + LAMDA))
152 POWER4 = POWER4 * 0.25e0
H A Ddrjval.f85 DOUBLE PRECISION POWER4,RC,RCX,RF,RN,RNDEV,SIGMA,S1,S2,S3,SN,THIRD local
186 POWER4 = 1.0d0
218 SIGMA = SIGMA + POWER4 * RC
219 POWER4 = POWER4 * 0.25d0
236 RJ = 3.0d0 * SIGMA + POWER4 * (S1 + S2 + S3) / (MU * SQRT(MU))
H A Dsrjval.f85 REAL POWER4,RC,RCX,RF,RN,RNDEV,SIGMA,S1,S2,S3,SN,THIRD local
186 POWER4 = 1.0e0
218 SIGMA = SIGMA + POWER4 * RC
219 POWER4 = POWER4 * 0.25e0
236 RJ = 3.0e0 * SIGMA + POWER4 * (S1 + S2 + S3) / (MU * SQRT(MU))
/dports/math/slatec/src/
H A Ddrd.f316 DOUBLE PRECISION MU, POWER4, SIGMA, S1, S2, X, XN, XNDEV
382 POWER4 = 1.0D0
394 SIGMA = SIGMA + POWER4/(ZNROOT*(ZN+LAMDA))
395 POWER4 = POWER4*0.250D0
408 DRD = 3.0D0*SIGMA + POWER4*(1.0D0+S1+S2)/(MU*SQRT(MU))
H A Drd.f314 REAL MU, POWER4, SIGMA, S1, S2, X, XN, XNDEV
379 POWER4 = 1.0E0
391 SIGMA = SIGMA + POWER4/(ZNROOT*(ZN+LAMDA))
392 POWER4 = POWER4*0.250E0
405 RD = 3.0E0*SIGMA + POWER4*(1.0E0+S1+S2)/(MU* SQRT(MU))
H A Ddrj.f303 DOUBLE PRECISION POWER4, DRC, SIGMA, S1, S2, S3, X, XN, XNDEV
371 POWER4 = 1.0D0
387 SIGMA = SIGMA + POWER4*DRC(ALFA,BETA,IER)
388 POWER4 = POWER4*0.250D0
403 DRJ = 3.0D0*SIGMA + POWER4*(S1+S2+S3)/(MU* SQRT(MU))
H A Drj.f307 REAL POWER4, RC, SIGMA, S1, S2, S3, X, XN, XNDEV
375 POWER4 = 1.0E0
391 SIGMA = SIGMA + POWER4*RC(ALFA,BETA,IER)
392 POWER4 = POWER4*0.250E0
407 RJ = 3.0E0*SIGMA + POWER4*(S1+S2+S3)/(MU* SQRT(MU))
/dports/editors/hte/ht-e9e63373148da5d7df397d8075740d8c096ecb1d/asm/
H A Dppcopc.cc1209 #define POWER4 PPC_OPCODE_POWER4 macro
2020 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2021 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2217 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2218 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
2222 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2223 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
2227 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2514 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
2887 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/math/cmlib/cmlib-3.0_8/src/fcnpak/
H A Drj.f293 REAL POWER4, RC, SIGMA, S1, S2, S3, X, XN, XNDEV
372 POWER4 = 1.0E0
390 SIGMA = SIGMA + POWER4*RC(ALFA,BETA,IER)
391 POWER4 = POWER4*0.250E0
408 RJ = 3.0E0*SIGMA + POWER4*(S1+S2+S3)/(MU* SQRT(MU))
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Dppc-opc.c1778 #define POWER4 PPC_OPCODE_POWER4 macro
1828 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
2889 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2891 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2895 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2897 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2901 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3275 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3566 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
4432 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Dppc-opc.c1824 #define POWER4 PPC_OPCODE_POWER4 macro
1876 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
2937 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2939 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2943 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2945 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2949 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3325 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3618 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
4480 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dppc-opc.c1759 #define POWER4 PPC_OPCODE_POWER4 macro
1809 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
2835 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2837 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2841 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2843 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2847 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3220 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3510 { "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
4378 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dppc-opc.c1759 #define POWER4 PPC_OPCODE_POWER4 macro
1809 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
2835 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2837 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2841 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2843 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2847 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3220 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3510 { "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
4378 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/security/beecrypt/beecrypt-4.2.1/
H A DBENCHMARKS34 BeeCrypt 4.1.2 | gcc-3.3.3 | SuSE Enterprise 9 | POWER4 1000 | 16 GB: 5620
37 BeeCrypt 3.0.0 | gcc-3.x | RedHat Linux | POWER4+ 1200 | : 2592
55 BeeCrypt 4.1.2 | gcc-3.3.3 | SuSE Enterprise 9 | POWER4 1000 | 16 GB: 43.9 MB…
62 BeeCrypt 4.1.2 | gcc-3.3.3 | SuSE Enterprise 9 | POWER4 1000 | 16 GB: 51.2 MB…
69 BeeCrypt 4.1.2 | gcc-3.3.3 | SuSE Enterprise 9 | POWER4 1000 | 16 GB: 32.8 MB…
74 BeeCrypt 4.1.0 | gcc-3.3.3 | SuSE Enterprise 9 | POWER4 1000 | 16 GB: 57.6 MB…
76 BeeCrypt 4.1.2 | gcc-3.3.3 | SuSE Enterprise 9 | POWER4 1000 | 16 GB: 57.9 MB…
/dports/emulators/qemu/qemu-6.2.0/disas/
H A Dppc.c1958 #define POWER4 PPC_OPCODE_POWER4 macro
2015 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
3080 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3082 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3086 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3088 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3092 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3475 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3782 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
4695 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/emulators/qemu42/qemu-4.2.1/disas/
H A Dppc.c1958 #define POWER4 PPC_OPCODE_POWER4 macro
2015 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
3080 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3082 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3086 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3088 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3092 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3475 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3782 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
4695 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/
H A Dppc-dis.c1954 #define POWER4 PPC_OPCODE_POWER4 macro
2008 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
3069 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3071 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3075 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3077 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3081 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3464 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3762 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
4675 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/emulators/qemu5/qemu-5.2.0/disas/
H A Dppc.c1958 #define POWER4 PPC_OPCODE_POWER4 macro
2015 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
3080 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3082 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3086 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3088 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3092 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3475 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3782 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
4695 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/emulators/qemu60/qemu-6.0.0/disas/
H A Dppc.c1958 #define POWER4 PPC_OPCODE_POWER4 macro
2015 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
3080 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3082 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3086 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3088 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3092 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3475 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3782 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
4695 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/
H A Dppc.c1955 #define POWER4 PPC_OPCODE_POWER4 macro
2012 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
3077 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3079 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3083 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3085 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3089 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3472 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3777 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
4690 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/ppc/gnu/
H A Dppc-opc.c1836 #define POWER4 PPC_OPCODE_POWER4 macro
1898 {"attn", X(0,256), X_MASK, POWER4, {0}},
2888 {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, {0}},
2889 {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, {0}},
2890 {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, {0}},
2891 {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, {0}},
3431 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, {RT, FXM4}},
3738 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, {RB, L}},
4728 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}},
4798 {"lq", OP(56), OP_MASK, POWER4, {RTQ, DQ, RAQ}},
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/disas/
H A Dppc.c1958 #define POWER4 PPC_OPCODE_POWER4 macro
2015 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
3080 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3082 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3086 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3088 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3092 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3475 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3782 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
4695 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/
H A Dppc.c1958 #define POWER4 PPC_OPCODE_POWER4 macro
2015 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
3080 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3082 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3086 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3088 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3092 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3475 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3782 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
4695 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
[all …]

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