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Searched refs:PPCPMR (Results 1 – 25 of 41) sorted by relevance

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/dports/devel/vasm/vasm/cpus/ppc/
H A Dcpu.h131 #define PPCPMR CPU_TYPE_PMR macro
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dppc-opc.c1785 #define PPCPMR PPC_OPCODE_PMR macro
3581 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3697 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4008 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4066 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Dppc-opc.c1804 #define PPCPMR PPC_OPCODE_PMR macro
3637 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3753 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4064 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4122 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dppc-opc.c1785 #define PPCPMR PPC_OPCODE_PMR macro
3581 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3697 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4008 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4066 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Dppc-opc.c1852 #define PPCPMR PPC_OPCODE_PMR macro
3689 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3801 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4112 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4170 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/emulators/qemu/qemu-6.2.0/disas/
H A Dppc.c1991 #define PPCPMR PPC_OPCODE_PMR macro
3853 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3966 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4291 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4349 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/emulators/qemu42/qemu-4.2.1/disas/
H A Dppc.c1991 #define PPCPMR PPC_OPCODE_PMR macro
3853 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3966 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4291 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4349 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/
H A Dppc-dis.c1984 #define PPCPMR PPC_OPCODE_PMR macro
3833 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3946 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4271 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4329 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/emulators/qemu5/qemu-5.2.0/disas/
H A Dppc.c1991 #define PPCPMR PPC_OPCODE_PMR macro
3853 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3966 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4291 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4349 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/emulators/qemu60/qemu-6.0.0/disas/
H A Dppc.c1991 #define PPCPMR PPC_OPCODE_PMR macro
3853 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3966 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4291 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4349 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/
H A Dppc.c1988 #define PPCPMR PPC_OPCODE_PMR macro
3848 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3961 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4286 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4344 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/ppc/gnu/
H A Dppc-opc.c1870 #define PPCPMR PPC_OPCODE_PMR macro
3812 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, {RT, PMR}},
3908 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, {RT}},
4116 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, {PMR, RS}},
4209 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, {RS}},
/dports/emulators/qemu-utils/qemu-4.2.1/disas/
H A Dppc.c1991 #define PPCPMR PPC_OPCODE_PMR macro
3853 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3966 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4291 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4349 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/
H A Dppc.c1991 #define PPCPMR PPC_OPCODE_PMR macro
3853 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3966 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4291 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4349 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/
H A Dppc.c1991 #define PPCPMR PPC_OPCODE_PMR macro
3853 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3966 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4291 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4349 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/
H A Dppc.c1991 #define PPCPMR PPC_OPCODE_PMR macro
3853 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3966 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
4291 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4349 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Dppc-opc.c1942 #define PPCPMR PPC_OPCODE_PMR macro
3884 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}},
3980 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}},
4203 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}},
4296 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}},
/dports/devel/gdb761/gdb-7.6.1/opcodes/
H A Dppc-opc.c2721 #define PPCPMR PPC_OPCODE_PMR macro
4695 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}},
4792 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}},
5032 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}},
5126 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}},
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/
H A Dppc-opc.c3046 #define PPCPMR PPC_OPCODE_PMR macro
5254 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5355 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5612 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5710 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/
H A Dppc-opc.c3046 #define PPCPMR PPC_OPCODE_PMR macro
5254 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5355 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5612 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5710 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/xmon/
H A Dppc-opc.c2994 #define PPCPMR PPC_OPCODE_PMR macro
5192 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5293 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5548 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5646 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/xmon/
H A Dppc-opc.c2994 #define PPCPMR PPC_OPCODE_PMR macro
5192 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5293 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5548 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5646 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
/dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/xmon/
H A Dppc-opc.c2994 #define PPCPMR PPC_OPCODE_PMR macro
5192 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5293 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5548 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5646 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/
H A Dppc-opc.c4313 #define PPCPMR PPC_OPCODE_PMR macro
6847 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
6988 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, EXT, {RT}},
7324 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
7465 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, EXT, {RS}},
/dports/devel/gdb/gdb-11.1/opcodes/
H A Dppc-opc.c4313 #define PPCPMR PPC_OPCODE_PMR macro
6847 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
6988 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, EXT, {RT}},
7324 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
7465 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, EXT, {RS}},

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