/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | ppc-opc.c | 1788 #define PPCRFMCI PPC_OPCODE_RFMCI macro 2896 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3707 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3709 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3710 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3711 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4013 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4014 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4015 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | ppc-opc.c | 1807 #define PPCRFMCI PPC_OPCODE_RFMCI macro 2950 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3763 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3765 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3766 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3767 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4069 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4070 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4071 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | ppc-opc.c | 1788 #define PPCRFMCI PPC_OPCODE_RFMCI macro 2896 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3707 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3709 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3710 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3711 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4013 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4014 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4015 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | ppc-opc.c | 1855 #define PPCRFMCI PPC_OPCODE_RFMCI macro 2998 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3811 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3813 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3814 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3815 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4117 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4118 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4119 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/emulators/qemu/qemu-6.2.0/disas/ |
H A D | ppc.c | 1994 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3141 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3976 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3978 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3979 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3980 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4296 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4297 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4298 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/emulators/qemu42/qemu-4.2.1/disas/ |
H A D | ppc.c | 1994 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3141 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3976 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3978 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3979 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3980 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4296 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4297 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4298 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/ |
H A D | ppc-dis.c | 1987 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3130 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3956 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3958 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3959 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3960 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4276 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4277 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4278 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/emulators/qemu5/qemu-5.2.0/disas/ |
H A D | ppc.c | 1994 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3141 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3976 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3978 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3979 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3980 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4296 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4297 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4298 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/emulators/qemu60/qemu-6.0.0/disas/ |
H A D | ppc.c | 1994 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3141 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3976 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3978 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3979 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3980 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4296 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4297 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4298 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/ |
H A D | ppc.c | 1991 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3138 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3971 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3973 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3974 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3975 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4291 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4292 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4293 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/ppc/gnu/ |
H A D | ppc-opc.c | 1873 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3099 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI, {0}}, 3917 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, {RT}}, 3918 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, {RT}}, 3919 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, {RT}}, 3920 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, {RT}}, 4212 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, {RS}}, 4213 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, {RS}}, 4214 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, {RS}},
|
/dports/emulators/qemu-utils/qemu-4.2.1/disas/ |
H A D | ppc.c | 1994 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3141 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3976 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3978 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3979 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3980 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4296 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4297 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4298 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/ |
H A D | ppc.c | 1994 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3141 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3976 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3978 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3979 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3980 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4296 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4297 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4298 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/ |
H A D | ppc.c | 1994 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3141 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3976 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3978 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3979 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3980 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4296 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4297 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4298 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/ |
H A D | ppc.c | 1994 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3141 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3976 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3978 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3979 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3980 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 4296 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4297 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4298 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/ |
H A D | ppc-opc.c | 1944 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3166 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}}, 3989 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, 3990 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, 3991 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, 3992 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, 4299 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, 4300 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, 4301 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
|
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | ppc-opc.c | 3049 #define PPCRFMCI PPC_OPCODE_RFMCI macro 4434 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, 5364 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5365 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5366 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5367 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, 5713 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5714 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5715 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, 7049 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
|
H A D | ChangeLog | 201 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
|
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | ppc-opc.c | 3049 #define PPCRFMCI PPC_OPCODE_RFMCI macro 4434 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, 5364 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5365 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5366 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5367 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, 5713 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5714 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5715 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, 7049 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
|
H A D | ChangeLog | 201 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
|
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/xmon/ |
H A D | ppc-opc.c | 2997 #define PPCRFMCI PPC_OPCODE_RFMCI macro 4380 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, 5302 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5303 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5304 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5305 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, 5649 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5650 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5651 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, 6989 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
|
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/xmon/ |
H A D | ppc-opc.c | 2997 #define PPCRFMCI PPC_OPCODE_RFMCI macro 4380 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, 5302 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5303 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5304 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5305 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, 5649 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5650 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5651 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, 6989 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
|
/dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/xmon/ |
H A D | ppc-opc.c | 2997 #define PPCRFMCI PPC_OPCODE_RFMCI macro 4380 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, 5302 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5303 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5304 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5305 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, 5649 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5650 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5651 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, 6989 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
|
/dports/devel/gdb761/gdb-7.6.1/opcodes/ |
H A D | ppc-opc.c | 2724 #define PPCRFMCI PPC_OPCODE_RFMCI macro 3959 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}}, 4801 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, 4802 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, 4803 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, 4804 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, 5129 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE, {RS}}, 5130 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE, {RS}}, 5131 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
|
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | ppc-opc.c | 4316 #define PPCRFMCI PPC_OPCODE_RFMCI macro 5882 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, 6999 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, EXT, {RT}}, 7000 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, EXT, {RT}}, 7001 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, EXT, {RT}}, 7002 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN|EXT, {RT}}, 7470 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, EXT, {RS}}, 7471 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, EXT, {RS}}, 7472 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, EXT, {RS}}, 9026 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
|