/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/gma500/ |
H A D | psb_lid.c | 31 } while ((pp_status & PP_ON) == 0 && in psb_lid_timer_func() 34 if (REG_READ(PP_STATUS) & PP_ON) { in psb_lid_timer_func() 47 } while ((pp_status & PP_ON) == 0); in psb_lid_timer_func()
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H A D | psb_intel_lvds.c | 225 } while ((pp_status & PP_ON) == 0); in psb_intel_lvds_set_power() 236 } while (pp_status & PP_ON); in psb_intel_lvds_set_power() 325 } while ((pp_status & PP_ON) == 0); in psb_intel_lvds_restore() 331 } while (pp_status & PP_ON); in psb_intel_lvds_restore()
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H A D | oaktrail_lvds.c | 50 } while ((pp_status & (PP_ON | PP_READY)) == PP_READY); in oaktrail_lvds_set_power() 61 } while (pp_status & PP_ON); in oaktrail_lvds_set_power()
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H A D | cdv_intel_lvds.c | 119 } while ((pp_status & PP_ON) == 0); in cdv_intel_lvds_set_power() 130 } while (pp_status & PP_ON); in cdv_intel_lvds_set_power()
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H A D | psb_intel_reg.h | 151 # define PP_ON (1 << 31) macro
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H A D | cdv_intel_dp.c | 419 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE; in cdv_intel_edp_panel_on() 445 u32 pp, idle_off_mask = PP_ON ; in cdv_intel_edp_panel_off()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/gma500/ |
H A D | psb_lid.c | 31 } while ((pp_status & PP_ON) == 0 && in psb_lid_timer_func() 34 if (REG_READ(PP_STATUS) & PP_ON) { in psb_lid_timer_func() 47 } while ((pp_status & PP_ON) == 0); in psb_lid_timer_func()
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H A D | psb_intel_lvds.c | 225 } while ((pp_status & PP_ON) == 0); in psb_intel_lvds_set_power() 236 } while (pp_status & PP_ON); in psb_intel_lvds_set_power() 325 } while ((pp_status & PP_ON) == 0); in psb_intel_lvds_restore() 331 } while (pp_status & PP_ON); in psb_intel_lvds_restore()
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H A D | oaktrail_lvds.c | 50 } while ((pp_status & (PP_ON | PP_READY)) == PP_READY); in oaktrail_lvds_set_power() 61 } while (pp_status & PP_ON); in oaktrail_lvds_set_power()
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H A D | cdv_intel_lvds.c | 119 } while ((pp_status & PP_ON) == 0); in cdv_intel_lvds_set_power() 130 } while (pp_status & PP_ON); in cdv_intel_lvds_set_power()
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H A D | psb_intel_reg.h | 151 # define PP_ON (1 << 31) macro
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/gma500/ |
H A D | psb_lid.c | 31 } while ((pp_status & PP_ON) == 0 && in psb_lid_timer_func() 34 if (REG_READ(PP_STATUS) & PP_ON) { in psb_lid_timer_func() 47 } while ((pp_status & PP_ON) == 0); in psb_lid_timer_func()
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H A D | psb_intel_lvds.c | 225 } while ((pp_status & PP_ON) == 0); in psb_intel_lvds_set_power() 236 } while (pp_status & PP_ON); in psb_intel_lvds_set_power() 325 } while ((pp_status & PP_ON) == 0); in psb_intel_lvds_restore() 331 } while (pp_status & PP_ON); in psb_intel_lvds_restore()
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H A D | oaktrail_lvds.c | 50 } while ((pp_status & (PP_ON | PP_READY)) == PP_READY); in oaktrail_lvds_set_power() 61 } while (pp_status & PP_ON); in oaktrail_lvds_set_power()
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H A D | cdv_intel_lvds.c | 119 } while ((pp_status & PP_ON) == 0); in cdv_intel_lvds_set_power() 130 } while (pp_status & PP_ON); in cdv_intel_lvds_set_power()
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H A D | psb_intel_reg.h | 151 # define PP_ON (1 << 31) macro
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/i915/display/ |
H A D | intel_pps.c | 236 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; in vlv_pipe_has_pp_on() 411 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power() 443 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 444 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_I… 446 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 449 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
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H A D | intel_lvds.c | 321 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) in intel_enable_lvds() 338 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) in intel_disable_lvds()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/i915/display/ |
H A D | intel_pps.c | 236 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; in vlv_pipe_has_pp_on() 411 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power() 443 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 444 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_I… 446 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 449 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
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H A D | intel_lvds.c | 321 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) in intel_enable_lvds() 338 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) in intel_disable_lvds()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/i915/display/ |
H A D | intel_pps.c | 236 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; in vlv_pipe_has_pp_on() 411 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power() 443 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 444 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_I… 446 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 449 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
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H A D | intel_lvds.c | 321 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) in intel_enable_lvds() 338 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) in intel_disable_lvds()
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/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/i915/ |
H A D | intel_lvds.c | 228 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) in intel_enable_lvds() 254 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) in intel_disable_lvds()
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H A D | intel_dp.c | 330 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power() 1031 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1032 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_I… 1034 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1037 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
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/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm/dist/shared-core/ |
H A D | i915_reg.h | 716 #define PP_ON (1 << 31) macro
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