Searched refs:PSR_MASK (Results 1 – 8 of 8) sorted by relevance
/dports/games/libretro-fbneo/FBNeo-bbe3c05/src/cpu/arm/ |
H A D | arm.cpp | 135 #define PSR_MASK ((UINT32) 0xf0000000u) macro 430 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in ArmRun() 471 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state() 479 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state() 606 R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15 & MODE_MASK); in HandleMemSingle() 833 R15 = (rd & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15&MODE_MASK); in HandleALU() 847 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 873 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 938 …SetRegister( 15, (R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv+=4))&ADDRESS_MAS… in loadInc() 962 … *deferredR15=(R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv-=4))&ADDRESS_MASK); in loadDec()
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/dports/games/libretro-fbalpha/fbalpha-84eb9d9/src/cpu/arm/ |
H A D | arm.cpp | 135 #define PSR_MASK ((UINT32) 0xf0000000u) macro 427 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in ArmRun() 463 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state() 471 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state() 598 R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15 & MODE_MASK); in HandleMemSingle() 825 R15 = (rd & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15&MODE_MASK); in HandleALU() 839 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 865 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 930 …SetRegister( 15, (R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv+=4))&ADDRESS_MAS… in loadInc() 954 … *deferredR15=(R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv-=4))&ADDRESS_MASK); in loadDec()
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/dports/emulators/mess/mame-mame0226/src/devices/cpu/arm/ |
H A D | arm.cpp | 117 #define PSR_MASK ((uint32_t) 0xf0000000u) macro 433 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in execute_run() 465 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state() 474 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state() 666 … R15 = (cpu_read32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15 & MODE_MASK); in HandleMemSingle() 915 R15 = (rd & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15&MODE_MASK); in HandleALU() 929 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 955 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 1028 …SetRegister( 15, (R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((cpu_read32(rbv+=4))&ADDRESS… in loadInc() 1055 …*deferredR15=(R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((cpu_read32(rbv-=4))&ADDRESS_MAS… in loadDec()
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/dports/emulators/mame/mame-mame0226/src/devices/cpu/arm/ |
H A D | arm.cpp | 117 #define PSR_MASK ((uint32_t) 0xf0000000u) macro 433 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in execute_run() 465 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state() 474 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state() 666 … R15 = (cpu_read32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15 & MODE_MASK); in HandleMemSingle() 915 R15 = (rd & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15&MODE_MASK); in HandleALU() 929 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 955 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 1028 …SetRegister( 15, (R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((cpu_read32(rbv+=4))&ADDRESS… in loadInc() 1055 …*deferredR15=(R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((cpu_read32(rbv-=4))&ADDRESS_MAS… in loadDec()
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/dports/games/libretro-mame2003_plus/mame2003-plus-libretro-17e9889/src/cpu/arm/ |
H A D | arm.c | 117 #define PSR_MASK ((data32_t) 0xf0000000u) macro 409 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in arm_execute() 554 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state() 562 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state() 824 R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & MODE_MASK); in HandleMemSingle() 1052 R15 = (rd & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15&MODE_MASK); in HandleALU() 1066 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 1098 SetRegister(15, (rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 1150 …SetRegister( 15, (R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv+=4))&ADDRESS_MAS… in loadInc() 1174 … *deferredR15=(R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv-=4))&ADDRESS_MASK); in loadDec()
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/dports/games/libretro-mame2003/mame2003-libretro-4358db4/src/cpu/arm/ |
H A D | arm.c | 116 #define PSR_MASK ((data32_t) 0xfc000000u) macro 399 R15 = (pc&PSR_MASK)|0x8|eARM_MODE_SVC|(pc&MODE_MASK); in arm_execute() 542 R15 = (pc&PSR_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set PC=0x1c */ in arm_check_irq_state() 549 R15 = (pc&PSR_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=0x18 */ in arm_check_irq_state() 810 R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & MODE_MASK); in HandleMemSingle() 1034 R15 = (rd & ADDRESS_MASK) | (R15 & PSR_MASK) | oldMode; in HandleALU() 1113 SetRegister( 15, (R15&PSR_MASK) | (R15&MODE_MASK) | ((READ32(rbv+=4))&ADDRESS_MASK) ); in loadInc() 1136 SetRegister( 15, (R15&PSR_MASK) | (R15&MODE_MASK) | ((READ32(rbv-=4))&ADDRESS_MASK) ); in loadDec()
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/dports/devel/avr-gdb/gdb-7.3.1/sim/cr16/ |
H A D | simops.c | 99 PSR_MASK = (PSR_I_BIT enumerator 111 PSR_HW_MASK = (PSR_MASK) 172 val &= PSR_MASK; in move_to_cr()
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/dports/devel/gdb761/gdb-7.6.1/sim/cr16/ |
H A D | simops.c | 99 PSR_MASK = (PSR_I_BIT enumerator 111 PSR_HW_MASK = (PSR_MASK) 172 val &= PSR_MASK; in move_to_cr()
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