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Searched refs:PWR_CPUCR_PDDS_D1 (Results 1 – 5 of 5) sorted by relevance

/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/src/
H A Dstm32h7xx_hal_pwr.c440 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1); in HAL_PWR_EnterSTOPMode()
444 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1); in HAL_PWR_EnterSTOPMode()
486 SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1); in HAL_PWR_EnterSTANDBYMode()
490 SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1); in HAL_PWR_EnterSTANDBYMode()
H A Dstm32h7xx_hal_pwr_ex.c544 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1); in HAL_PWREx_EnterSTOPMode()
674 SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D1); in HAL_PWREx_EnterSTANDBYMode()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/inc/
H A Dstm32h7xx_ll_pwr.h136 #define LL_PWR_CPU_MODE_D1STANDBY PWR_CPUCR_PDDS_D1 /*!< Enter D1 domain to Standby mode wh…
818 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode); in LL_PWR_CPU_SetD1PowerMode()
845 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1)); in LL_PWR_CPU_GetD1PowerMode()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_h7xx/
H A Dstm32h753xx.h14286 #define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk /*!< D1 domain Power… macro
H A Dstm32h743xx.h14017 #define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk /*!< D1 domain Power… macro