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Searched refs:PopInst (Results 1 – 25 of 34) sorted by relevance

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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp317 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
389 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
392 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
412 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
417 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
422 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
429 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp317 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
389 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
392 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
412 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
417 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
422 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
429 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
H A DR600MachineScheduler.h89 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp317 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
389 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
392 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
412 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
417 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
422 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
429 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
H A DR600MachineScheduler.h89 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp312 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
384 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
387 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
407 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
412 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
417 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
424 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp312 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
384 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
387 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
407 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
412 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
417 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
424 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp312 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
384 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
387 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
407 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
412 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
417 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
424 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp317 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
389 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
392 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
412 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
417 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
422 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
429 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
H A DR600MachineScheduler.h89 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp317 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
389 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
392 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
412 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
417 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
422 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
429 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
H A DR600MachineScheduler.h89 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp312 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
384 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
387 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
407 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
412 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
417 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
424 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp312 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
384 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
387 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
407 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
412 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
417 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
424 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp312 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
384 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
387 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
407 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
412 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
417 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
424 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp317 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
389 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
392 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
412 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
417 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
422 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
429 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
H A DR600MachineScheduler.h89 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp312 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
384 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
387 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
407 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
412 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
417 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
424 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp312 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
384 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
387 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
407 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
412 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
417 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
424 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp317 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
389 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
392 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
412 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
417 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
422 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
429 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
H A DR600MachineScheduler.h89 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp318 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
390 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
393 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
413 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
418 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
423 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
430 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
H A DR600MachineScheduler.h90 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp317 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
389 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
392 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
412 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
417 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
422 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
429 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
H A DR600MachineScheduler.h90 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);

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