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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/
H A DPeiPchPolicyLib.c160 UINTN PortIndex; in LoadPcieRpConfigDefault() local
175 for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { in LoadPcieRpConfigDefault()
181 PcieRpConfig->RootPort[PortIndex].PhysicalSlotNumber = (UINT8) PortIndex; in LoadPcieRpConfigDefault()
233 UINTN PortIndex; in LoadSataConfigDefault() local
248 for (PortIndex = 0; PortIndex < GetPchMaxSataPortNum (); PortIndex++) { in LoadSataConfigDefault()
744 UINTN PortIndex; in LoadUsbConfigDefault() local
754 for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) { in LoadUsbConfigDefault()
755 UsbConfig->PortUsb20[PortIndex].Enable = TRUE; in LoadUsbConfigDefault()
758 for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { in LoadUsbConfigDefault()
786 for (PortIndex = 0; PortIndex < PCH_H_XHCI_MAX_USB2_PORTS; PortIndex++) { in LoadUsbConfigDefault()
[all …]
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2TbltDevicePkg/PlatformDxe/
H A DIchPlatformPolicy.c63 UINT8 PortIndex; in InitPchPlatformPolicy() local
173 for (PortIndex = 0; PortIndex < PCH_USB_MAX_PHYSICAL_PORTS; PortIndex++) { in InitPchPlatformPolicy()
174 …DxePlatformPchPolicy->UsbConfig->PortSettings[PortIndex].Enable = mSystemConfiguration.PchUsbPort[… in InitPchPlatformPolicy()
245 for (PortIndex = 0; PortIndex < PCH_PCIE_MAX_ROOT_PORTS; PortIndex++) { in InitPchPlatformPolicy()
246 …Policy->PciExpressConfig->RootPort[PortIndex].Enable = mSystemConfiguration… in InitPchPlatformPolicy()
248 …DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].FunctionNumber = PortIn… in InitPchPlatformPolicy()
249 …DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].PhysicalSlotNumber = PortIn… in InitPchPlatformPolicy()
269 for (PortIndex = 0; PortIndex < PCH_AHCI_MAX_PORTS; PortIndex++) { in InitPchPlatformPolicy()
271 DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable = PCH_DEVICE_ENABLE; in InitPchPlatformPolicy()
282 if(0 == PortIndex){ in InitPchPlatformPolicy()
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/
H A DIchPlatformPolicy.c51 UINT8 PortIndex; in InitPchPlatformPolicy() local
161 for (PortIndex = 0; PortIndex < PCH_USB_MAX_PHYSICAL_PORTS; PortIndex++) { in InitPchPlatformPolicy()
162 …DxePlatformPchPolicy->UsbConfig->PortSettings[PortIndex].Enable = mSystemConfiguration.PchUsbPort[… in InitPchPlatformPolicy()
233 for (PortIndex = 0; PortIndex < PCH_PCIE_MAX_ROOT_PORTS; PortIndex++) { in InitPchPlatformPolicy()
234 …Policy->PciExpressConfig->RootPort[PortIndex].Enable = mSystemConfiguration… in InitPchPlatformPolicy()
236 …DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].FunctionNumber = PortIn… in InitPchPlatformPolicy()
237 …DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].PhysicalSlotNumber = PortIn… in InitPchPlatformPolicy()
257 for (PortIndex = 0; PortIndex < PCH_AHCI_MAX_PORTS; PortIndex++) { in InitPchPlatformPolicy()
259 DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable = PCH_DEVICE_ENABLE; in InitPchPlatformPolicy()
270 if(0 == PortIndex){ in InitPchPlatformPolicy()
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/PeiDxeSmmPchInitCommonLib/
H A DPchRpfn.c30 UINT8 PortIndex; in PchConfigureRpfnMapping() local
60 for (PortIndex = 0; PortIndex < MaxPciePortNum; ) { in PchConfigureRpfnMapping()
61 GetPchPcieRpDevFun (PortIndex, &DevNum, &FuncNum); in PchConfigureRpfnMapping()
72 ControllerIndex = PortIndex / 4; in PchConfigureRpfnMapping()
73 OriginalFuncZeroRp = (PortIndex / 8) * 8; in PchConfigureRpfnMapping()
79 …ControllerPcd[ControllerIndex] &= (UINT32) ~(B_PCH_PCR_SPX_PCD_RP1FN << ((PortIndex % 4) * S_PCH_P… in PchConfigureRpfnMapping()
91 PsfSetPcieFunctionWithS3BootScript (PortIndex, 0); in PchConfigureRpfnMapping()
96 PortIndex = ((PortIndex / 8) + 1) * 8; in PchConfigureRpfnMapping()
102 PortIndex++; in PchConfigureRpfnMapping()
/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/
H A DPeiFspPchPolicyInitLib.c143 IN UINT8 PortIndex, in UpdateUsb20OverCurrentPolicy() argument
150 UsbConfig->PortUsb20[PortIndex].OverCurrentPin, in UpdateUsb20OverCurrentPolicy()
154 if (PortIndex >= MAX_USB2_PORTS) { in UpdateUsb20OverCurrentPolicy()
173 IN UINT8 PortIndex, in UpdateUsb30OverCurrentPolicy() argument
180 UsbConfig->PortUsb30[PortIndex].OverCurrentPin, in UpdateUsb30OverCurrentPolicy()
184 if (PortIndex >= MAX_USB2_PORTS) { in UpdateUsb30OverCurrentPolicy()
204 UINTN PortIndex; in UpdatePchUsbConfig() local
208 for (PortIndex = 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortIndex++) { in UpdatePchUsbConfig()
209 …UPDATE_POLICY (FspsUpd->FspsConfig.PortUsb20Enable[PortIndex], UsbConfig->PortUsb20[PortIndex].Ena… in UpdatePchUsbConfig()
211 for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { in UpdatePchUsbConfig()
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Pch/PchInit/Smm/
H A DPchPcieSmm.c44 IN UINT8 PortIndex,
107 &mPcieRootPortConfig[PortIndex].PcieRpCommonConfig,
193 UINT32 PortIndex;
199 for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) {
200 RpBase = PchPcieRpPciCfgBase (PortIndex);
206 PchPcieRpDevNumber (PortIndex),
207 PchPcieRpFuncNumber (PortIndex),
281 UINT8 PortIndex;
352 for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) {
353 RpBase = PchPcieRpPciCfgBase (PortIndex);
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/
H A DPchPcieSmm.c38 IN UINT8 PortIndex, in PchPcieSmi() argument
69 mLtrNonSupportRpBitMap &= ~(1 << PortIndex); in PchPcieSmi()
81 (BOOLEAN)mPcieRootPortConfig[PortIndex].EnableCpm in PchPcieSmi()
84 mLtrNonSupportRpBitMap |= 1 << PortIndex; in PchPcieSmi()
179 UINT32 PortIndex; in PchPciePmIoTrapSmiCallback() local
206 for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) { in PchPciePmIoTrapSmiCallback()
295 UINT8 PortIndex; in InitializePchPcieSmm() local
357 for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) { in InitializePchPcieSmm()
379 PortIndex, in InitializePchPcieSmm()
387 PortIndex, in InitializePchPcieSmm()
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/
H A DPchPcieSmm.c41 IN UINT8 PortIndex, in PchPcieSmi() argument
103 &mPcieRootPortConfig[PortIndex], in PchPcieSmi()
187 UINT32 PortIndex; in PchPciePmIoTrapSmiCallback() local
195 for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) { in PchPciePmIoTrapSmiCallback()
196 GetPchPcieRpDevFun (PortIndex, &RpDevice, &RpFunction); in PchPciePmIoTrapSmiCallback()
207 &mPcieRootPortConfig[PortIndex], in PchPciePmIoTrapSmiCallback()
278 UINT8 PortIndex; in InitializePchPcieSmm() local
337 for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) { in InitializePchPcieSmm()
356 PortIndex, in InitializePchPcieSmm()
364 PortIndex, in InitializePchPcieSmm()
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/
H A DCpuPcieSmm.c52 UINT32 PortIndex;
60 for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) {
61 GetCpuPcieRpDevFun (PortIndex, &RpDevice, &RpFunction);
74 &mCpuPcieRootPortConfig[PortIndex].PcieRpCommonConfig,
95 IN UINT8 PortIndex,
165 &mCpuPcieRootPortConfig[PortIndex].PcieRpCommonConfig,
310 UINT8 PortIndex;
356 for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) {
357 GetCpuPcieRpDevFun (PortIndex, &RpDevice, &RpFunction);
375 (PortIndex + CpuRpIndex0),
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/
H A DPeiPchPolicyUpdate.c88 IN UINT8 PortIndex, in UpdateUsb20AfePolicy() argument
113 IN UINT8 PortIndex, in UpdateUsb20OverCurrentPolicy() argument
118 UsbConfig->PortUsb20[PortIndex].OverCurrentPin = Pin; in UpdateUsb20OverCurrentPolicy()
120 if (PortIndex >= MAX_USB2_PORTS) { in UpdateUsb20OverCurrentPolicy()
138 IN UINT8 PortIndex, in UpdateUsb30OverCurrentPolicy() argument
145 if (PortIndex >= MAX_USB2_PORTS) { in UpdateUsb30OverCurrentPolicy()
164 UINTN PortIndex; in UpdatePchUsbConfig() local
168 for (PortIndex = 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortIndex++) { in UpdatePchUsbConfig()
169 UsbConfig->PortUsb20[PortIndex].Enable = TRUE; in UpdatePchUsbConfig()
171 for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { in UpdatePchUsbConfig()
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/
H A DPeiPchPolicyUpdate.c88 IN UINT8 PortIndex, in UpdateUsb20AfePolicy() argument
113 IN UINT8 PortIndex, in UpdateUsb20OverCurrentPolicy() argument
118 UsbConfig->PortUsb20[PortIndex].OverCurrentPin = Pin; in UpdateUsb20OverCurrentPolicy()
120 if (PortIndex >= MAX_USB2_PORTS) { in UpdateUsb20OverCurrentPolicy()
138 IN UINT8 PortIndex, in UpdateUsb30OverCurrentPolicy() argument
145 if (PortIndex >= MAX_USB2_PORTS) { in UpdateUsb30OverCurrentPolicy()
164 UINTN PortIndex; in UpdatePchUsbConfig() local
168 for (PortIndex = 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortIndex++) { in UpdatePchUsbConfig()
169 UsbConfig->PortUsb20[PortIndex].Enable = TRUE; in UpdatePchUsbConfig()
171 for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { in UpdatePchUsbConfig()
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/
H A DPeiPchPolicyLib.c134 UINTN PortIndex; in LoadSataConfigDefault() local
152 for (PortIndex = 0; PortIndex < GetPchMaxSataPortNum (SataCtrlIndex); PortIndex++) { in LoadSataConfigDefault()
576 UINTN PortIndex; in LoadUsbConfigDefault() local
586 for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) { in LoadUsbConfigDefault()
587 UsbConfig->PortUsb20[PortIndex].Enable = TRUE; in LoadUsbConfigDefault()
590 for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { in LoadUsbConfigDefault()
591 UsbConfig->PortUsb30[PortIndex].Enable = TRUE; in LoadUsbConfigDefault()
603 for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) { in LoadUsbConfigDefault()
604 UsbConfig->PortUsb20[PortIndex].Afe.Petxiset = 3; in LoadUsbConfigDefault()
605 UsbConfig->PortUsb20[PortIndex].Afe.Txiset = 2; in LoadUsbConfigDefault()
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/dports/audio/fatfrog-lv2/FatFrog.lv2-1.0/libxputty/xputty/lv2_plugin/
H A Dlv2_plugin.h69 void plugin_value_changed(X11_UI *ui, Widget_t *w, PortIndex index);
81 Widget_t* add_my_knob(Widget_t *w, PortIndex index, const char * label,
85 Widget_t* add_my_image_knob(Widget_t *w, PortIndex index, const char * label,
89 Widget_t* add_my_value_knob(Widget_t *w, PortIndex index, const char * label,
92 Widget_t* add_my_switch_image(Widget_t *w, PortIndex index, const char * label,
96 Widget_t* add_my_combobox(Widget_t *w, PortIndex index, const char * label, const char** items,
/dports/audio/littlefly-lv2/LittleFly.lv2-1.0/libxputty/xputty/lv2_plugin/
H A Dlv2_plugin.h69 void plugin_value_changed(X11_UI *ui, Widget_t *w, PortIndex index);
81 Widget_t* add_my_knob(Widget_t *w, PortIndex index, const char * label,
85 Widget_t* add_my_image_knob(Widget_t *w, PortIndex index, const char * label,
89 Widget_t* add_my_value_knob(Widget_t *w, PortIndex index, const char * label,
92 Widget_t* add_my_switch_image(Widget_t *w, PortIndex index, const char * label,
96 Widget_t* add_my_combobox(Widget_t *w, PortIndex index, const char * label, const char** items,
/dports/audio/guitarix-lv2/guitarix-0.43.1/src/LV2/xputty/lv2_plugin/
H A Dlv2_plugin.h68 void plugin_value_changed(X11_UI *ui, Widget_t *w, PortIndex index);
80 Widget_t* add_my_knob(Widget_t *w, PortIndex index, const char * label,
84 Widget_t* add_my_image_knob(Widget_t *w, PortIndex index, const char * label,
88 Widget_t* add_my_value_knob(Widget_t *w, PortIndex index, const char * label,
91 Widget_t* add_my_switch_image(Widget_t *w, PortIndex index, const char * label,
95 Widget_t* add_my_combobox(Widget_t *w, PortIndex index, const char * label, const char** items,
/dports/audio/mamba/Mamba-2.2/libxputty/xputty/lv2_plugin/
H A Dlv2_plugin.h69 void plugin_value_changed(X11_UI *ui, Widget_t *w, PortIndex index);
81 Widget_t* add_my_knob(Widget_t *w, PortIndex index, const char * label,
85 Widget_t* add_my_image_knob(Widget_t *w, PortIndex index, const char * label,
89 Widget_t* add_my_value_knob(Widget_t *w, PortIndex index, const char * label,
92 Widget_t* add_my_switch_image(Widget_t *w, PortIndex index, const char * label,
96 Widget_t* add_my_combobox(Widget_t *w, PortIndex index, const char * label, const char** items,
/dports/audio/fluida-lv2/Fluida.lv2-0.7/libxputty/xputty/lv2_plugin/
H A Dlv2_plugin.h69 void plugin_value_changed(X11_UI *ui, Widget_t *w, PortIndex index);
81 Widget_t* add_my_knob(Widget_t *w, PortIndex index, const char * label,
85 Widget_t* add_my_image_knob(Widget_t *w, PortIndex index, const char * label,
89 Widget_t* add_my_value_knob(Widget_t *w, PortIndex index, const char * label,
92 Widget_t* add_my_switch_image(Widget_t *w, PortIndex index, const char * label,
96 Widget_t* add_my_combobox(Widget_t *w, PortIndex index, const char * label, const char** items,
/dports/audio/ardour6/Ardour-6.8.0/libs/ardour/
H A Dport_engine_shared.cc194 , _ports (new PortIndex) in PortEngineSharedImpl()
220 boost::shared_ptr<PortIndex> p = _ports.reader (); in get_ports()
252 boost::shared_ptr<PortIndex> p = _ports.reader(); in get_physical_outputs()
265 boost::shared_ptr<PortIndex> p = _ports.reader(); in get_physical_inputs()
281 boost::shared_ptr<PortIndex> p = _ports.reader(); in n_physical_outputs()
305 boost::shared_ptr<PortIndex> p = _ports.reader(); in n_physical_inputs()
340 RCUWriter<PortIndex> index_writer (_ports); in add_port()
359 RCUWriter<PortIndex> index_writer (_ports); in unregister_port()
392 RCUWriter<PortIndex> index_writer (_ports); in unregister_ports()
400 PortIndex::iterator cur = i++; in unregister_ports()
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/
H A DPcieInitLib.c1139 UINT32 PortIndex = PcieCfg->PortIndex;
1141 if (PortIndex >= PCIE_MAX_ROOTBRIDGE) {
1147 … mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][PortIndex];
1152 … mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex);
1176 (VOID)PciePcsInit(soctype, HostBridgeNum, PortIndex);
1179 (VOID)PcieSpdSet(soctype, HostBridgeNum, PortIndex, 3);
1182 (VOID)PcieSetupRC(PortIndex,PcieCfg->PortInfo.PortWidth);
1191 (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex);
1205 PcieRegWrite(PortIndex, 0x10, 0);
1208 while (!PcieIsLinkUp(soctype, HostBridgeNum, PortIndex)) {
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/PeiDxeSmmPchPsfPrivateLib/
H A DPchPsfPrivateLib.c963 UINTN PortIndex; in PsfReloadDefaultPcieRpDevFunc() local
966 PortIndex = 0; in PsfReloadDefaultPcieRpDevFunc()
981 for (; PortIndex < 8; PortIndex++) { in PsfReloadDefaultPcieRpDevFunc()
984 Psf1RpFuncCfgBase + 4 * (UINT16) PortIndex, in PsfReloadDefaultPcieRpDevFunc()
986 ((PortIndex % 8) << N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION) in PsfReloadDefaultPcieRpDevFunc()
992 for (; PortIndex < 16 && PortIndex < MaxPciePorts; PortIndex++) { in PsfReloadDefaultPcieRpDevFunc()
995 Psf1RpFuncCfgBase + 4 * (UINT16) PortIndex, in PsfReloadDefaultPcieRpDevFunc()
997 ((PortIndex % 8) << N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION) in PsfReloadDefaultPcieRpDevFunc()
1003 for (; PortIndex < MaxPciePorts; PortIndex++) { in PsfReloadDefaultPcieRpDevFunc()
1006 Psf1RpFuncCfgBase + 4 * (UINT16) PortIndex, in PsfReloadDefaultPcieRpDevFunc()
[all …]
/dports/audio/guitarix-lv2/guitarix-0.43.1/src/LV2/gx_barkgraphiceq.lv2/
H A Dgx_barkgraphiceq_ui.cpp58 void plugin_value_changed(X11_UI *ui, Widget_t *w, PortIndex index) { in plugin_value_changed()
72 Widget_t* add_my_slider(Widget_t *w, PortIndex index, const char * label, in add_my_slider()
89 int port = (PortIndex) V1; in plugin_create_controller_widgets()
100 port = (PortIndex) G1; in plugin_create_controller_widgets()
105 …ui->widget[iw] = add_my_slider(ui->widget[iw], (PortIndex)port,ps->frequencys[iw], ui,w_pos, 180, … in plugin_create_controller_widgets()
/dports/audio/lvtk/lvtk-2.0.0rc1-14-g1028f69/lvtk/ext/ui/
H A Dport_map.hpp28 struct PortIndex : FeatureData<LV2UI_Port_Map> { struct
29 PortIndex() : FeatureData (LV2_UI__portMap) {} in PortIndex() function
62 PortIndex port_index;
/dports/audio/guitarix-lv2/guitarix-0.43.1/src/LV2/gx_mbcompressor.lv2/
H A Dgx_mbcompressor_ui.cpp235 void plugin_value_changed(X11_UI *ui, Widget_t *w, PortIndex index) { in plugin_value_changed()
249 switch ((PortIndex)port_index) in check_multi_controller()
346 Widget_t* add_my_slider(Widget_t *w, PortIndex index, const char * label, in add_my_slider()
388 int port = (PortIndex) V1; in plugin_create_controller_widgets()
402 port = (PortIndex) MAKEUP1; in plugin_create_controller_widgets()
404 ui->widget[iw] = add_my_knob(ui->widget[iw], (PortIndex)port,"Makeup", ui,w_pos, 0, 60, 85); in plugin_create_controller_widgets()
412 port = (PortIndex) MAKEUPTHRESHOLD1; in plugin_create_controller_widgets()
422 port = (PortIndex) RATIO1; in plugin_create_controller_widgets()
432 port = (PortIndex) ATTACK1; in plugin_create_controller_widgets()
442 port = (PortIndex) RELEASE1; in plugin_create_controller_widgets()
[all …]
/dports/audio/noise-suppression-for-voice-lv2/noise-suppression-for-voice-0.91-2-g6466b34/src/lv2_plugin/
H A DRnNoiseLv2Plugin.cpp18 const auto portIdx = static_cast<PortIndex>(port); in connect_port()
21 case PortIndex::input: { in connect_port()
25 case PortIndex::output: { in connect_port()
/dports/audio/fomp-lv2/fomp-1.2.2/src/
H A Dmvclpf24.h34 virtual void setport (PortIndex port, PortData *data);
55 virtual void setport (PortIndex port, PortData *data);
76 virtual void setport (PortIndex port, PortData *data);
98 virtual void setport (PortIndex port, PortData *data);

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