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Searched refs:QL_LDST_X32 (Results 1 – 8 of 8) sorted by relevance

/dports/devel/gdb761/gdb-7.6.1/opcodes/
H A Daarch64-tbl.h1028 #define QL_LDST_X32 \ macro
1937 {"ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
1949 …rsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0},
1962 {"ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0},
1973 {"ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
1995 …00000, 0xffe00c00, ldst_unscaled, OP_LDURSW, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, F_HAS_ALIAS},
1996 …{"ldrsw", 0xb8800000, 0xffe00c00, ldst_unscaled, 0, CORE, OP2 (Rt, ADDR_SIMM9_2), QL_LDST_X32, F_A…
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/
H A Daarch64-tbl.h1155 #define QL_LDST_X32 \ macro
2300 CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
2312 …0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0, NULL},
2325 CORE_INSN ("ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0),
2336 CORE_INSN ("ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
2348 …xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0, NULL},
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/
H A Daarch64-tbl.h1155 #define QL_LDST_X32 \ macro
2300 CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
2312 …0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0, NULL},
2325 CORE_INSN ("ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0),
2336 CORE_INSN ("ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
2348 …xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0, NULL},
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/arm/aarch64/
H A Daarch64-tbl.h1191 #define QL_LDST_X32 \ macro
3157 CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
3169 …N ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0),
3182 …CORE_INSN ("ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0),
3193 …CORE_INSN ("ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
3205 …("ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/
H A Daarch64-tbl.h1216 #define QL_LDST_X32 \ macro
3525 CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
3546 …N ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0),
3559 …CORE_INSN ("ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0),
3570 …CORE_INSN ("ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
3582 …("ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
/dports/devel/gdb/gdb-11.1/opcodes/
H A Daarch64-tbl.h1216 #define QL_LDST_X32 \ macro
3525 CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
3546 …N ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0),
3559 …CORE_INSN ("ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0),
3570 …CORE_INSN ("ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
3582 …("ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
/dports/devel/gnulibiberty/binutils-2.37/opcodes/
H A Daarch64-tbl.h1216 #define QL_LDST_X32 \ macro
3525 CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
3546 …N ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0),
3559 …CORE_INSN ("ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0),
3570 …CORE_INSN ("ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
3582 …("ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
/dports/devel/binutils/binutils-2.37/opcodes/
H A Daarch64-tbl.h1216 #define QL_LDST_X32 \ macro
3525 CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
3546 …N ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0),
3559 …CORE_INSN ("ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0),
3570 …CORE_INSN ("ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
3582 …("ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),