Home
last modified time | relevance | path

Searched refs:RADEON_LAYOUT_TILED (Results 1 – 25 of 88) sorted by relevance

1234

/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/r300/
H A Dr300_texture_desc.c63 assert(macrotile <= RADEON_LAYOUT_TILED); in r300_get_pixel_alignment()
95 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); in r300_texture_macro_switch()
230 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED && in r300_setup_miptree()
233 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; in r300_setup_miptree()
478 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
479 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
505 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
520 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/r300/
H A Dr300_texture_desc.c63 assert(macrotile <= RADEON_LAYOUT_TILED); in r300_get_pixel_alignment()
95 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); in r300_texture_macro_switch()
230 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED && in r300_setup_miptree()
233 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; in r300_setup_miptree()
478 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
479 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
505 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
520 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/r300/
H A Dr300_texture_desc.c63 assert(macrotile <= RADEON_LAYOUT_TILED); in r300_get_pixel_alignment()
95 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); in r300_texture_macro_switch()
230 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED && in r300_setup_miptree()
233 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; in r300_setup_miptree()
478 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
479 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
505 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
520 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/r300/
H A Dr300_texture_desc.c63 assert(macrotile <= RADEON_LAYOUT_TILED); in r300_get_pixel_alignment()
95 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); in r300_texture_macro_switch()
230 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED && in r300_setup_miptree()
233 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; in r300_setup_miptree()
478 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
479 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
505 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
520 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/r300/
H A Dr300_texture_desc.c63 assert(macrotile <= RADEON_LAYOUT_TILED); in r300_get_pixel_alignment()
95 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); in r300_texture_macro_switch()
230 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED && in r300_setup_miptree()
233 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; in r300_setup_miptree()
478 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
479 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
505 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
520 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/r300/
H A Dr300_texture_desc.c63 assert(macrotile <= RADEON_LAYOUT_TILED); in r300_get_pixel_alignment()
95 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); in r300_texture_macro_switch()
230 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED && in r300_setup_miptree()
233 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; in r300_setup_miptree()
478 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
479 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
505 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
520 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/r300/
H A Dr300_texture_desc.c63 assert(macrotile <= RADEON_LAYOUT_TILED); in r300_get_pixel_alignment()
95 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); in r300_texture_macro_switch()
230 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED && in r300_setup_miptree()
233 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; in r300_setup_miptree()
478 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
479 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
505 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
520 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/r300/
H A Dr300_texture_desc.c63 assert(macrotile <= RADEON_LAYOUT_TILED); in r300_get_pixel_alignment()
95 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); in r300_texture_macro_switch()
230 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED && in r300_setup_miptree()
233 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; in r300_setup_miptree()
478 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
479 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
505 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
520 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/r300/
H A Dr300_texture_desc.c63 assert(macrotile <= RADEON_LAYOUT_TILED); in r300_get_pixel_alignment()
95 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); in r300_texture_macro_switch()
230 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED && in r300_setup_miptree()
233 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; in r300_setup_miptree()
478 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
479 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
505 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
520 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/r300/
H A Dr300_texture_desc.c63 assert(macrotile <= RADEON_LAYOUT_TILED); in r300_get_pixel_alignment()
95 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); in r300_texture_macro_switch()
230 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED && in r300_setup_miptree()
233 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; in r300_setup_miptree()
478 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
479 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
505 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
520 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/r300/
H A Dr300_texture_desc.c63 assert(macrotile <= RADEON_LAYOUT_TILED); in r300_get_pixel_alignment()
95 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); in r300_texture_macro_switch()
230 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED && in r300_setup_miptree()
233 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; in r300_setup_miptree()
478 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
479 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
505 tex->tex.microtile = RADEON_LAYOUT_TILED; in r300_setup_tiling()
520 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED; in r300_setup_tiling()
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c792 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
794 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
841 md->u.legacy.macrotile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
843 md->u.legacy.microtile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
/dports/lang/clover/mesa-21.3.6/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c926 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
928 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
977 md->u.legacy.macrotile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
979 md->u.legacy.microtile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c926 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
928 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
977 md->u.legacy.macrotile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
979 md->u.legacy.microtile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
/dports/graphics/libosmesa/mesa-21.3.6/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c926 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
928 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
977 md->u.legacy.macrotile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
979 md->u.legacy.microtile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
/dports/graphics/mesa-libs/mesa-21.3.6/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c926 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
928 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
977 md->u.legacy.macrotile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
979 md->u.legacy.microtile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c926 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
928 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
977 md->u.legacy.macrotile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
979 md->u.legacy.microtile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c926 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
928 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
977 md->u.legacy.macrotile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
979 md->u.legacy.microtile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c926 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
928 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
977 md->u.legacy.macrotile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
979 md->u.legacy.microtile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c926 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
928 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
977 md->u.legacy.macrotile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
979 md->u.legacy.microtile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
/dports/graphics/mesa-dri/mesa-21.3.6/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c926 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
928 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
977 md->u.legacy.macrotile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
979 md->u.legacy.microtile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c884 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
886 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) in radv_amdgpu_winsys_bo_set_metadata()
935 md->u.legacy.macrotile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
937 md->u.legacy.microtile = RADEON_LAYOUT_TILED; in radv_amdgpu_winsys_bo_get_metadata()
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/amd/vulkan/
H A Dradv_radeon_winsys.h129 RADEON_LAYOUT_TILED, enumerator
/dports/lang/clover/mesa-21.3.6/src/amd/vulkan/
H A Dradv_radeon_winsys.h118 RADEON_LAYOUT_TILED, enumerator
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/amd/vulkan/
H A Dradv_radeon_winsys.h118 RADEON_LAYOUT_TILED, enumerator

1234