| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 32 const MipsRegisterBankInfo &RBI);
44 const MipsRegisterBankInfo &RBI; member in __anon0ea3542c0111::MipsInstructionSelector
63 const MipsRegisterBankInfo &RBI) in MipsInstructionSelector() argument
65 TRI(*STI.getRegisterInfo()), RBI(RBI), in MipsInstructionSelector()
78 const RegisterBankInfo &RBI) { in selectCopy() argument
85 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
102 return selectCopy(I, TII, MRI, TRI, RBI); in select()
161 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in select()
163 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in select()
202 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in select()
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anonfead367a0111::ARMInstructionSelector
96 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
110 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), in ARMInstructionSelector()
148 const RegisterBankInfo &RBI) { in selectCopy() argument
158 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
675 return selectCopy(I, TII, MRI, TRI, RBI); in select()
790 return selectCopy(I, TII, MRI, TRI, RBI); in select()
840 return selectCopy(I, TII, MRI, TRI, RBI); in select()
917 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 116 const AArch64RegisterBankInfo &RBI; member in __anon2ce82f4e0111::AArch64InstructionSelector
137 const AArch64RegisterBankInfo &RBI) in AArch64InstructionSelector() argument
139 TRI(*STI.getRegisterInfo()), RBI(RBI), in AArch64InstructionSelector()
635 .constrainAllUses(TII, TRI, RBI); in selectCompareBranch()
760 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1107 if (unsupportedBinOp(I, RBI, MRI, TRI)) in select()
1143 if (unsupportedBinOp(I, RBI, MRI, TRI)) in select()
1277 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1356 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1364 return selectCopy(I, TII, MRI, TRI, RBI); in select()
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anon48063bfc0111::ARMInstructionSelector
132 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
146 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
184 const RegisterBankInfo &RBI) { in selectCopy() argument
194 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
733 return selectCopy(I, TII, MRI, TRI, RBI); in select()
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
898 return selectCopy(I, TII, MRI, TRI, RBI); in select()
975 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 106 const AArch64RegisterBankInfo &RBI; member in __anon0528c7cc0111::AArch64InstructionSelector
127 const AArch64RegisterBankInfo &RBI) in AArch64InstructionSelector() argument
129 TRI(*STI.getRegisterInfo()), RBI(RBI), in AArch64InstructionSelector()
143 const RegisterBankInfo &RBI, in getRegClassForTypeOnBank() argument
625 .constrainAllUses(TII, TRI, RBI); in selectCompareBranch()
750 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1080 if (unsupportedBinOp(I, RBI, MRI, TRI)) in select()
1116 if (unsupportedBinOp(I, RBI, MRI, TRI)) in select()
1250 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1329 return selectCopy(I, TII, MRI, TRI, RBI); in select()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anonef4d83510111::ARMInstructionSelector
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
213 const RegisterBankInfo &RBI) { in selectCopy() argument
223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1126 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anon9c8721660111::ARMInstructionSelector
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
177 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
215 const RegisterBankInfo &RBI) { in selectCopy() argument
225 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
850 return selectCopy(I, TII, MRI, TRI, RBI); in select()
961 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1033 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1128 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anon821e5b900111::ARMInstructionSelector
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
213 const RegisterBankInfo &RBI) { in selectCopy() argument
223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1126 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anoneb33d0c00111::ARMInstructionSelector
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
177 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
215 const RegisterBankInfo &RBI) { in selectCopy() argument
225 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
850 return selectCopy(I, TII, MRI, TRI, RBI); in select()
961 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1033 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1128 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anona2f339a40111::ARMInstructionSelector
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
213 const RegisterBankInfo &RBI) { in selectCopy() argument
223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1126 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 35 const ARMRegisterBankInfo &RBI);
75 const ARMRegisterBankInfo &RBI; member in __anon915f417e0111::ARMInstructionSelector
160 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
174 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
212 const RegisterBankInfo &RBI) { in selectCopy() argument
222 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
847 return selectCopy(I, TII, MRI, TRI, RBI); in select()
958 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1030 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1125 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anone5e3a99e0111::ARMInstructionSelector
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
213 const RegisterBankInfo &RBI) { in selectCopy() argument
223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1108 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anond791b9b40111::ARMInstructionSelector
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
213 const RegisterBankInfo &RBI) { in selectCopy() argument
223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1108 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anon9070bcb30111::ARMInstructionSelector
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
213 const RegisterBankInfo &RBI) { in selectCopy() argument
223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1108 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anonaf7afd310111::ARMInstructionSelector
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
213 const RegisterBankInfo &RBI) { in selectCopy() argument
223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1108 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anon1d3051660111::ARMInstructionSelector
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
213 const RegisterBankInfo &RBI) { in selectCopy() argument
223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1108 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anonfc5b73520111::ARMInstructionSelector
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
213 const RegisterBankInfo &RBI) { in selectCopy() argument
223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1108 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 36 const PPCRegisterBankInfo &RBI);
48 const PPCRegisterBankInfo &RBI; member in __anon3185d7170111::PPCInstructionSelector
67 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
69 TRI(*STI.getRegisterInfo()), RBI(RBI), in PPCInstructionSelector()
89 const PPCRegisterBankInfo &RBI) { in createPPCInstructionSelector() argument
90 return new PPCInstructionSelector(TM, Subtarget, RBI); in createPPCInstructionSelector()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 36 const PPCRegisterBankInfo &RBI);
48 const PPCRegisterBankInfo &RBI; member in __anonbb6601a40111::PPCInstructionSelector
67 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
69 TRI(*STI.getRegisterInfo()), RBI(RBI), in PPCInstructionSelector()
89 const PPCRegisterBankInfo &RBI) { in createPPCInstructionSelector() argument
90 return new PPCInstructionSelector(TM, Subtarget, RBI); in createPPCInstructionSelector()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 36 const PPCRegisterBankInfo &RBI);
48 const PPCRegisterBankInfo &RBI; member in __anon5fdfa53a0111::PPCInstructionSelector
67 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
69 TRI(*STI.getRegisterInfo()), RBI(RBI), in PPCInstructionSelector()
89 const PPCRegisterBankInfo &RBI) { in createPPCInstructionSelector() argument
90 return new PPCInstructionSelector(TM, Subtarget, RBI); in createPPCInstructionSelector()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 36 const PPCRegisterBankInfo &RBI);
48 const PPCRegisterBankInfo &RBI; member in __anon93154a160111::PPCInstructionSelector
67 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
69 TRI(*STI.getRegisterInfo()), RBI(RBI), in PPCInstructionSelector()
89 const PPCRegisterBankInfo &RBI) { in createPPCInstructionSelector() argument
90 return new PPCInstructionSelector(TM, Subtarget, RBI); in createPPCInstructionSelector()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 36 const PPCRegisterBankInfo &RBI);
48 const PPCRegisterBankInfo &RBI; member in __anon8c41b2f90111::PPCInstructionSelector
67 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
69 TRI(*STI.getRegisterInfo()), RBI(RBI), in PPCInstructionSelector()
89 const PPCRegisterBankInfo &RBI) { in createPPCInstructionSelector() argument
90 return new PPCInstructionSelector(TM, Subtarget, RBI); in createPPCInstructionSelector()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 36 const PPCRegisterBankInfo &RBI);
48 const PPCRegisterBankInfo &RBI; member in __anon50bd28f70111::PPCInstructionSelector
67 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
69 TRI(*STI.getRegisterInfo()), RBI(RBI), in PPCInstructionSelector()
89 const PPCRegisterBankInfo &RBI) { in createPPCInstructionSelector() argument
90 return new PPCInstructionSelector(TM, Subtarget, RBI); in createPPCInstructionSelector()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 36 const PPCRegisterBankInfo &RBI);
48 const PPCRegisterBankInfo &RBI; member in __anon2c5d036c0111::PPCInstructionSelector
67 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
69 TRI(*STI.getRegisterInfo()), RBI(RBI), in PPCInstructionSelector()
89 const PPCRegisterBankInfo &RBI) { in createPPCInstructionSelector() argument
90 return new PPCInstructionSelector(TM, Subtarget, RBI); in createPPCInstructionSelector()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 36 const PPCRegisterBankInfo &RBI);
48 const PPCRegisterBankInfo &RBI; member in __anon9d55d12a0111::PPCInstructionSelector
67 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
69 TRI(*STI.getRegisterInfo()), RBI(RBI), in PPCInstructionSelector()
89 const PPCRegisterBankInfo &RBI) { in createPPCInstructionSelector() argument
90 return new PPCInstructionSelector(TM, Subtarget, RBI); in createPPCInstructionSelector()
|