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Searched refs:RCC_PLL1DIVR_Q1_Msk (Results 1 – 2 of 2) sorted by relevance

/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_h7xx/
H A Dstm32h753xx.h14951 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
14952 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
H A Dstm32h743xx.h14682 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
14683 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk