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Searched refs:RD_CLK_POLARITY (Results 1 – 5 of 5) sorted by relevance

/dports/cad/yosys/yosys-yosys-0.12/tests/techmap/
H A Dmem_simple_4x1_map.v12 parameter RD_CLK_POLARITY = 1'b1; constant
57 if (RD_TRANSPARENT || !RD_CLK_ENABLE || !RD_CLK_POLARITY)
/dports/cad/yosys/yosys-yosys-0.12/techlibs/common/
H A Dsimlib.v2373 parameter RD_CLK_POLARITY = 1'b1; constant
2421 …[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_C…
2437 …if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], …
2460 parameter RD_CLK_POLARITY = 1'b1; constant
2519 …if (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[…
2553 …if (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && …
/dports/cad/yosys/yosys-yosys-0.12/kernel/
H A Dconstids.inc154 X(RD_CLK_POLARITY)
H A Dmem.cc197 cell->parameters[ID::RD_CLK_POLARITY] = rd_clk_polarity; in emit()
729 mrd.clk_polarity = cell->parameters.at(ID::RD_CLK_POLARITY).extract(i, 1).as_bool(); in mem_from_cell()
H A Drtlil.cc1552 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS))); in check()
1574 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS))); in check()