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Searched refs:REFCLK_CNTL (Results 1 – 21 of 21) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dccg.h37 SR(REFCLK_CNTL)
50 DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
51 DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dccg.h37 SR(REFCLK_CNTL)
50 DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
51 DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dccg.h37 SR(REFCLK_CNTL)
50 DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
51 DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.h37 SR(REFCLK_CNTL)
61 DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
62 DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
100 uint32_t REFCLK_CNTL; member
H A Ddcn20_dccg.c85 REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel); in dccg2_get_dccg_ref_freq()
H A Ddcn20_hwseq.c2449 if (REG(REFCLK_CNTL)) in dcn20_fpga_init_hw()
2450 REG_WRITE(REFCLK_CNTL, 0); in dcn20_fpga_init_hw()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.h37 SR(REFCLK_CNTL)
61 DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
62 DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
100 uint32_t REFCLK_CNTL; member
H A Ddcn20_dccg.c85 REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel); in dccg2_get_dccg_ref_freq()
H A Ddcn20_hwseq.c2449 if (REG(REFCLK_CNTL)) in dcn20_fpga_init_hw()
2450 REG_WRITE(REFCLK_CNTL, 0); in dcn20_fpga_init_hw()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.h37 SR(REFCLK_CNTL)
61 DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
62 DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
100 uint32_t REFCLK_CNTL; member
H A Ddcn20_dccg.c85 REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel); in dccg2_get_dccg_ref_freq()
H A Ddcn20_hwseq.c2449 if (REG(REFCLK_CNTL)) in dcn20_fpga_init_hw()
2450 REG_WRITE(REFCLK_CNTL, 0); in dcn20_fpga_init_hw()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_hwseq.h164 SR(REFCLK_CNTL), \
362 SR(REFCLK_CNTL), \
513 uint32_t REFCLK_CNTL; member
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_hwseq.h164 SR(REFCLK_CNTL), \
362 SR(REFCLK_CNTL), \
513 uint32_t REFCLK_CNTL; member
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_hwseq.h164 SR(REFCLK_CNTL), \
362 SR(REFCLK_CNTL), \
513 uint32_t REFCLK_CNTL; member
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hwseq.c441 REG_WRITE(REFCLK_CNTL, 0); in dcn30_init_hw()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hwseq.c441 REG_WRITE(REFCLK_CNTL, 0); in dcn30_init_hw()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hwseq.c441 REG_WRITE(REFCLK_CNTL, 0); in dcn30_init_hw()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c1286 REG_WRITE(REFCLK_CNTL, 0); in dcn10_init_hw()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c1286 REG_WRITE(REFCLK_CNTL, 0); in dcn10_init_hw()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c1286 REG_WRITE(REFCLK_CNTL, 0); in dcn10_init_hw()