| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 15 #define REGS_AHB2_BASE 0x03000000 macro
49 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
51 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
52 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
53 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
55 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
56 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
64 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
65 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
66 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
[all …]
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun9i.h | 14 #define REGS_AHB2_BASE 0x03000000 macro
58 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
60 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
61 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
62 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
64 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
65 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
73 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
74 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
75 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
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