/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | tic80-opc.c | 394 #define REG_22 (REG_0_E + 1) macro 399 #define REG_22_E (REG_22 + 1) 677 {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, 963 {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, 991 {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, 1139 …x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, 1140 …x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, 1154 …(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, 1155 …0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, 1182 …x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, [all …]
|
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | tic80-opc.c | 394 #define REG_22 (REG_0_E + 1) macro 399 #define REG_22_E (REG_22 + 1) 677 {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, 963 {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, 991 {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, 1139 …x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, 1140 …x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, 1154 …(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, 1155 …0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, 1182 …x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, [all …]
|
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | tic80-opc.c | 399 #define REG_22 (REG_0_E + 1) macro 404 #define REG_22_E (REG_22 + 1) 682 {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, 968 {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, 996 {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, 1144 …x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, 1145 …x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, 1159 …(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, 1160 …0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, 1187 …x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, [all …]
|
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/ |
H A D | tic80-opc.c | 399 #define REG_22 (REG_0_E + 1) macro 404 #define REG_22_E (REG_22 + 1) 682 {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, 968 {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, 996 {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, 1144 …x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, 1145 …x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, 1159 …(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, 1160 …0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, 1187 …x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, [all …]
|
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|
/dports/devel/gdb761/gdb-7.6.1/opcodes/ |
H A D | tic80-opc.c | 400 #define REG_22 (REG_0_E + 1) macro 405 #define REG_22_E (REG_22 + 1) 683 {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, 969 {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, 997 {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, 1145 …x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, 1146 …x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, 1160 …(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, 1161 …0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, 1188 …x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, [all …]
|
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | tic80-opc.c | 399 #define REG_22 (REG_0_E + 1) macro 404 #define REG_22_E (REG_22 + 1) 682 {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, 968 {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, 996 {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, 1144 …x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, 1145 …x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, 1159 …(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, 1160 …0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, 1187 …x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, [all …]
|
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | tic80-opc.c | 399 #define REG_22 (REG_0_E + 1) macro 404 #define REG_22_E (REG_22 + 1) 682 {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, 968 {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, 996 {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, 1144 …x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, 1145 …x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, 1159 …(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, 1160 …0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, 1187 …x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, [all …]
|
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | tic80-opc.c | 399 #define REG_22 (REG_0_E + 1) macro 404 #define REG_22_E (REG_22 + 1) 682 {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, 968 {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, 996 {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, 1144 …x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, 1145 …x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, 1159 …(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, 1160 …0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, 1187 …x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, [all …]
|
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/video/fbdev/ |
H A D | stifb.c | 138 #define REG_22 0x0005a0 macro 304 WRITE_WORD(0xffffffff, fb, REG_22); in CRX24_SET_OVLY_MASK() 425 WRITE_WORD(mask, fb, REG_22)
|
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/video/fbdev/ |
H A D | stifb.c | 138 #define REG_22 0x0005a0 macro 304 WRITE_WORD(0xffffffff, fb, REG_22); in CRX24_SET_OVLY_MASK() 425 WRITE_WORD(mask, fb, REG_22)
|
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/video/fbdev/ |
H A D | stifb.c | 138 #define REG_22 0x0005a0 macro 304 WRITE_WORD(0xffffffff, fb, REG_22); in CRX24_SET_OVLY_MASK() 425 WRITE_WORD(mask, fb, REG_22)
|
/dports/security/libfprint/libfprint-0.7.0/libfprint/drivers/ |
H A D | etes603.c | 91 #define REG_22 0x22 /* Normal gain (def: 0x21) */ macro 1229 msg_set_regs(dev, 4, REG_21, 0x23, REG_22, 0x21); in m_tunedc_state() 1363 REG_20, 0x00, REG_21, 0x23, REG_22, 0x21, REG_23, 0x20, in m_init_state()
|
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|
/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|
/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|
/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | ChangeLog-9297 | 1042 changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
|