1 struct addrmode addrmodes[] = {
2 MODE_Dn,-1, /* 0 */
3 MODE_An,-1,
4 MODE_AnIndir,-1,
5 MODE_AnPostInc,-1,
6 MODE_AnPreDec,-1,
7 MODE_An16Disp,-1,
8 MODE_An8Format,-1, /* 6 */
9 MODE_Extended,REG_AbsShort, /* 7 */
10 MODE_Extended,REG_AbsLong,
11 MODE_Extended,REG_PC16Disp,
12 MODE_Extended,REG_PC8Format,
13 MODE_Extended,REG_Immediate,
14 MODE_Extended,REG_RnList,
15 MODE_Extended,REG_FPnList, /* 13 */
16 MODE_FPn,-1,
17 MODE_SpecReg,-1 /* 15 */
18 };
19
20
21 /* specregs.h */
22 enum {
23 REG_CCR=0,REG_SR,REG_NC,REG_DC,REG_IC,REG_BC,
24
25 REG_ACC,REG_ACC0,REG_ACC1,REG_ACC2,REG_ACC3,REG_ACCX01,REG_ACCX23,
26 REG_MACSR,REG_MASK,REG_SFLEFT,REG_SFRIGHT,
27
28 REG_VX00,REG_VX01,REG_VX02,REG_VX03,REG_VX04,REG_VX05,REG_VX06,REG_VX07,
29 REG_VX08,REG_VX09,REG_VX10,REG_VX11,REG_VX12,REG_VX13,REG_VX14,REG_VX15,
30 REG_VX16,REG_VX17,REG_VX18,REG_VX19,REG_VX20,REG_VX21,REG_VX22,REG_VX23,
31
32 REG_TC,REG_SRP,REG_CRP,REG_DRP,REG_CAL,REG_VAL,REG_SCC,REG_AC,
33 REG_BAC0,REG_BAC1,REG_BAC2,REG_BAC3,REG_BAC4,REG_BAC5,REG_BAC6,REG_BAC7,
34 REG_BAD0,REG_BAD1,REG_BAD2,REG_BAD3,REG_BAD4,REG_BAD5,REG_BAD6,REG_BAD7,
35 REG_MMUSR,REG_PSR,REG_PCSR,REG_TT0,REG_TT1,
36 #if 0
37 REG_ACUSR,REG_AC0,REG_AC1,
38 #endif
39
40 /* MOVEC control registers _CTRL */
41 REG_SFC,REG_DFC,REG_CACR,REG_ASID,REG_TC_,
42 REG_ITT0,REG_ITT1,REG_DTT0,REG_DTT1,
43 REG_IACR0,REG_IACR1,REG_DACR0,REG_DACR1,
44 REG_ACR0,REG_ACR1,REG_ACR2,REG_ACR3,
45 REG_BUSCR,REG_MMUBAR,
46 REG_STR,REG_STC,REG_STH,REG_STB,REG_MWR,
47 REG_USP,REG_VBR,REG_CAAR,REG_MSP,
48 REG_ISP,REG_MMUSR_,REG_URP,REG_SRP_,REG_PCR,
49 REG_CCC,REG_IEP1,REG_IEP2,REG_BPC,REG_BPW,REG_DCH,REG_DCM,
50 REG_ROMBAR,REG_ROMBAR0,REG_ROMBAR1,
51 REG_RAMBAR,REG_RAMBAR0,REG_RAMBAR1,
52 REG_MPCR,REG_EDRAMBAR,REG_SECMBAR,REG_MBAR,
53 REG_PCR1U0,REG_PCR1L0,REG_PCR2U0,REG_PCR2L0,REG_PCR3U0,REG_PCR3L0,
54 REG_PCR1U1,REG_PCR1L1,REG_PCR2U1,REG_PCR2L1,REG_PCR3U1,REG_PCR3L1,
55 };
56
57
58 #define _(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p) \
59 ((a)|((b)<<1)|((c)<<2)|((d)<<3)|((e)<<4)|((f)<<5)|((g)<<6)|((h)<<7)| \
60 ((i)<<8)|((j)<<9)|((k)<<10)|((l)<<11)|((m)<<12)|((n)<<13)| \
61 ((o)<<14)|((p)<<15))
62
63 enum {
64 OP_D8=1,OP_D16,OP_D32,OP_D64,OP_F32,OP_F64,OP_F96,
65 D_,A_,B_,AI,IB,R_,RM,DD,CS,VDR2,VDR4,PA,AP,DP,
66 F_,FF,FR,FPIAR,IM,QI,IR,BR,AB,VA,M6,RL,FL,FS,
67 AY,AM,MA,MI,FA,CF,MAQ,CFAM,CM,AL,DA,DN,CFDA,CT,AC,AD,CFAD,
68 BD,BS,AK,MS,MR,CFMM,CFMN,ND,NI,NJ,NK,BY,BI,BJ,
69 _CCR,_SR,_USP,_CACHES,_ACC,_MACSR,_MASK,_CTRL,_ACCX,_AEXT,
70 _VAL,_FC,_RP_030,_RP_851,_TC,_AC,_M1_B,_BAC,_BAD,_PSR,_PCSR,
71 _TT,SH,VX,VXR2,VXR4
72 };
73
74 struct optype optypes[] = {
75 0,0,0,0,
76
77 /* OP_D8 8-bit data */
78 _(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA,0,0,
79
80 /* OP_D16 16-bit data */
81 _(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA,0,0,
82
83 /* OP_D32 32-bit data */
84 _(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA,0,0,
85
86 /* OP_D64 64-bit data */
87 _(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA|OTF_QUADIMM,0,0,
88
89 /* OP_F32 32-bit data */
90 _(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA|OTF_FLTIMM,0,0,
91
92 /* OP_F64 64-bit data */
93 _(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA|OTF_FLTIMM,0,0,
94
95 /* OP_F96 96-bit data */
96 _(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA|OTF_FLTIMM,0,0,
97
98 /* D_ data register */
99 _(1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
100
101 /* A_ address register */
102 _(0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
103
104 /* B_ (Apollo) base register */
105 _(0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),FL_BnReg,0,0,
106
107 /* AI address register indirect */
108 _(0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
109
110 /* IB (Apollo) base register indirect */
111 _(0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0),FL_BnReg,0,0,
112
113 /* R_ any data or address register */
114 _(1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
115
116 /* RM any data or address register with optional U/L extension (MAC) */
117 _(1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),FL_MAC,0,0,
118
119 /* DD double data register */
120 _(1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),FL_DoubleReg,0,0,
121
122 /* CS any double data or address register indirect (cas2) */
123 _(0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0),FL_DoubleReg,0,0,
124
125 /* VDR2 (Apollo) Dn:Dn+1 */
126 _(1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),OTF_VXRNG2,0,0,
127
128 /* VDR4 (Apollo) Dn-Dn+3 */
129 _(1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),OTF_VXRNG4,0,0,
130
131 /* PA address register indirect with predecrement */
132 _(0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
133
134 /* AP address register indirect with postincrement */
135 _(0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
136
137 /* DP address register indirect with displacement (movep) */
138 _(0,0,1,0,0,1,0,0,0,0,0,0,0,0,0,0),0,0,0,
139
140 /* F_ FPU register FPn */
141 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0),0,0,0,
142
143 /* FF double FPU register */
144 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0),FL_DoubleReg,0,0,
145
146 /* FR FPU special register FPCR/FPSR/FPIAR */
147 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0),FL_FPSpec,0,0,
148
149 /* FPIAR FPU special register FPIAR */
150 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0),OTF_CHKREG|FL_FPSpec,1,1,
151
152 /* IM immediate data */
153 _(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),0,0,0,
154
155 /* QI quick immediate data (moveq, addq, subq) */
156 _(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_NOSIZE,0,0,
157
158 /* IR immediate register list value (movem) */
159 _(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_NOSIZE,0,0,
160
161 /* BR branch destination */
162 _(0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),OTF_BRANCH,0,0,
163
164 /* AB absolute long destination */
165 _(0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),0,0,0,
166
167 /* VA absolute value */
168 _(0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),OTF_NOSIZE,0,0,
169
170 /* M6 mode 6 - addr. reg. indirect with index and displacement */
171 _(0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0),0,0,0,
172
173 /* RL An/Dn register list */
174 _(0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0),OTF_REGLIST,0,0,
175
176 /* FL FPn register list */
177 _(0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0),OTF_REGLIST,0,0,
178
179 /* FS FPIAR/FPSR/FPCR register list */
180 _(0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0),OTF_REGLIST|FL_FPSpec,0,0,
181
182 /* ea addressing modes */
183 /* AY all addressing modes 0-6,7.0-4 */
184 _(1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0),0,0,0,
185
186 /* AM alterable memory 2-6,7.0-1 */
187 _(0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0),0,0,0,
188
189 /* MA memory addressing modes 2-6,7.0-4 */
190 _(0,0,1,1,1,1,1,1,1,1,1,1,0,0,0,0),0,0,0,
191
192 /* MI memory addressing modes 2-6,7.0-3 without immediate */
193 _(0,0,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
194
195 /* FA memory addressing modes 2-6,7.0-4 with float immediate */
196 _(0,0,1,1,1,1,1,1,1,1,1,1,0,0,0,0),OTF_FLTIMM,0,0,
197
198 /* CF (ColdFire) float addressing modes 2-5 and 7.2 */
199 _(0,0,1,1,1,1,0,0,0,1,0,0,0,0,0,0),0,0,0,
200
201 /* MAQ memory addressing modes 2-6,7.0-4 with 64-bit immediate */
202 _(0,0,1,1,1,1,1,1,1,1,1,1,0,0,0,0),OTF_QUADIMM,0,0,
203
204 /* CFAM (ColdFire) alterable memory 2-5 */
205 _(0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0),0,0,0,
206
207 /* CM (ColdFire) alterable memory 2-5 with MASK-flag (MAC) */
208 _(0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0),FL_MAC,0,0,
209
210 /* AL alterable 0-6,7.0-1 */
211 _(1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0),0,0,0,
212
213 /* DA data 0,2-6,7.0-4 */
214 _(1,0,1,1,1,1,1,1,1,1,1,1,0,0,0,0),0,0,0,
215
216 /* DN data, but not immediate 0,2-6,7.0-3 */
217 _(1,0,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
218
219 /* CFDA (ColdFire) float data 0,2-6,7.0-4 (=CF + mode 0) */
220 _(1,0,1,1,1,1,0,0,0,1,0,0,0,0,0,0),0,0,0,
221
222 /* CT control, 2,5-6,7.0-3 */
223 _(0,0,1,0,0,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
224
225 /* AC alterable control, 2,5-6,7.0-1 */
226 _(0,0,1,0,0,1,1,1,1,0,0,0,0,0,0,0),0,0,0,
227
228 /* AD alterable data, 0,2-6,7.0-1 */
229 _(1,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0),0,0,0,
230
231 /* CFAD (ColdFire) alterable data, 0,2-5 */
232 _(1,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0),0,0,0,
233
234 /* BD alterable control or data (bitfield), 0,2,5-6,7.0-1 */
235 _(1,0,1,0,0,1,1,1,1,0,0,0,0,0,0,0),FL_Bitfield,0,0,
236
237 /* BS control or data register (bitfield), 0,2,5-6,7.0-3 */
238 _(1,0,1,0,0,1,1,1,1,1,1,0,0,0,0,0),FL_Bitfield,0,0,
239
240 /* AK alterable memory (incl. k-factor) 2-6,7.0-1 */
241 _(0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0),FL_KFactor,0,0,
242
243 /* MS save operands, 2,4-6,7.0-1 */
244 _(0,0,1,0,1,1,1,1,1,0,0,0,0,0,0,0),0,0,0,
245
246 /* MR restore operands, 2-3,5-6,7.0-3 */
247 _(0,0,1,1,0,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
248
249 /* CFMM (ColdFire) MOVEM, 2,5 */
250 _(0,0,1,0,0,1,0,0,0,0,0,0,0,0,0,0),0,0,0,
251
252 /* CFMN (ColdFire) FMOVEM src-ea, 2,5,7.2 */
253 _(0,0,1,0,0,1,0,0,0,1,0,0,0,0,0,0),0,0,0,
254
255 /* ND (Apollo) all except Dn, 1-6,7.0-4 */
256 _(0,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
257
258 /* NI (Apollo) all except immediate, 0-6,7.0-3 */
259 _(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
260
261 /* NJ (Apollo) all except Dn and immediate, 1-6,7.0-3 */
262 _(0,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
263
264 /* NK (Apollo) all except An and immediate, 0,2-6,7.0-3 */
265 _(1,0,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
266
267 /* BY (Apollo) all addressing modes 0-6,7.0-4 with An replaced by Bn */
268 _(1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0),FL_BnReg,0,0,
269
270 /* BI (Apollo) all except immediate, 0-6,7.0-3 with An repl. by Bn */
271 _(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0),FL_BnReg,0,0,
272
273 /* BJ (Apollo) all except Dn/An & immediate, 0-6,7.0-3, An -> Bn */
274 _(0,0,1,1,1,1,1,1,1,1,1,0,0,0,0,0),FL_BnReg,0,0,
275
276 /* special registers */
277 /* _CCR */
278 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_CCR,REG_CCR,
279 /* _SR */
280 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_SR,REG_SR,
281 /* _USP */
282 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_USP,REG_USP,
283 /* _CACHES */
284 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_NC,REG_BC,
285 /* _ACC */
286 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_ACC,REG_ACC,
287 /* _MACSR */
288 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_MACSR,REG_MACSR,
289 /* _MASK */
290 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_MASK,REG_MASK,
291 /* _CTRL */
292 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_SRRANGE|OTF_CHKREG,
293 REG_SFC,REG_PCR3L1,
294 /* _ACCX */
295 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_SRRANGE|OTF_CHKREG,
296 REG_ACC0,REG_ACC3,
297 /* _AEXT */
298 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_SRRANGE|OTF_CHKREG,
299 REG_ACCX01,REG_ACCX23,
300 /* _VAL */
301 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_VAL,REG_VAL,
302 /* _FC */
303 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_SFC,REG_DFC,
304 /* _RP_030 */
305 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_SRP,REG_CRP,
306 /* _RP_851 */
307 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_SRP,REG_DRP,
308 /* _TC */
309 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_TC,REG_TC,
310 /* _AC */
311 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_AC,REG_AC,
312 /* _M1_B */
313 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_CAL,REG_SCC,
314 /* _BAC */
315 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_BAC0,REG_BAC7,
316 /* _BAD */
317 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_BAD0,REG_BAD7,
318 /* _PSR */
319 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_MMUSR,REG_PSR,
320 /* _PCSR */
321 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_MMUSR,REG_PCSR,
322 /* _TT */
323 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_TT0,REG_TT1,
324 /* SH */
325 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_SFLEFT,REG_SFRIGHT,
326 /* VX (Apollo) */
327 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_SRRANGE|OTF_CHKREG,REG_VX00,REG_VX23,
328 /* VXR2 (Apollo) En:En+1 */
329 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_VXRNG2|OTF_SRRANGE|OTF_CHKREG,REG_VX00,REG_VX23,
330 /* VXR4 (Apollo) En-En+3 */
331 _(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_VXRNG4|OTF_SRRANGE|OTF_CHKREG,REG_VX00,REG_VX23,
332 };
333
334 #undef _
335
336
337 /* special operand insertion functions */
338
339 static void write_val(unsigned char *,int,int,taddr,int);
340
insert_cas2(unsigned char * d,struct oper_insert * i,operand * o)341 static void insert_cas2(unsigned char *d,struct oper_insert *i,operand *o)
342 {
343 uint16_t w1 = (*(d+2)<<8) | *(d+3);
344 uint16_t w2 = (*(d+4)<<8) | *(d+5);
345
346 w1 |= (i->size==4 ? o->reg&15 : o->reg&7) << (16-((i->pos-16)+i->size));
347 w2 |= (o->reg>>4) << (16-((i->pos-16)+i->size));
348 *(d+2) = w1>>8;
349 *(d+3) = w1&0xff;
350 *(d+4) = w2>>8;
351 *(d+5) = w2&0xff;
352 }
353
insert_macreg(unsigned char * d,struct oper_insert * i,operand * o)354 static void insert_macreg(unsigned char *d,struct oper_insert *i,operand *o)
355 {
356 if (i->pos == 4) {
357 /* special case: MSB is at bit-position 9 */
358 write_val(d,4,3,o->reg,0);
359 *(d+1) |= o->mode << 6;
360 }
361 else
362 write_val(d,i->pos,4,(o->mode<<3)+o->reg,0);
363 if (o->bf_offset) /* .u extension selects upper word, else lower */
364 *(d+3) |= i->size; /* size holds the U/L mask for this register */
365 }
366
insert_muldivl(unsigned char * d,struct oper_insert * i,operand * o)367 static void insert_muldivl(unsigned char *d,struct oper_insert *i,operand *o)
368 {
369 unsigned char r = o->reg & 7;
370
371 if (o->mode == MODE_An)
372 r |= REGAn;
373 *(d+2) |= r << 4;
374 *(d+3) |= r;
375 }
376
insert_divl(unsigned char * d,struct oper_insert * i,operand * o)377 static void insert_divl(unsigned char *d,struct oper_insert *i,operand *o)
378 {
379 *(d+2) |= o->reg & 0xf0;
380 *(d+3) |= o->reg & 0xf;
381 }
382
insert_tbl(unsigned char * d,struct oper_insert * i,operand * o)383 static void insert_tbl(unsigned char *d,struct oper_insert *i,operand *o)
384 {
385 *(d+1) |= o->reg & 7;
386 *(d+3) |= (o->reg & 0x70) >> 4;
387 }
388
insert_fp(unsigned char * d,struct oper_insert * i,operand * o)389 static void insert_fp(unsigned char *d,struct oper_insert *i,operand *o)
390 {
391 *(d+2) |= ((o->reg&7) << 2) | ((o->reg&7) >> 1);
392 *(d+3) |= (o->reg&1) << 7;
393 }
394
insert_fpcs(unsigned char * d,struct oper_insert * i,operand * o)395 static void insert_fpcs(unsigned char *d,struct oper_insert *i,operand *o)
396 {
397 *(d+2) |= (o->reg&0x60) >> 5;
398 *(d+3) |= ((o->reg&0x10) << 3) | (o->reg & 7);
399 }
400
insert_accx(unsigned char * d,struct oper_insert * i,operand * o)401 static void insert_accx(unsigned char *d,struct oper_insert *i,operand *o)
402 {
403 unsigned char v = o->extval[0];
404
405 *(d+1) |= (v&1) << 7;
406 *(d+3) |= (v&2) << 3;
407 }
408
insert_accx_rev(unsigned char * d,struct oper_insert * i,operand * o)409 static void insert_accx_rev(unsigned char *d,struct oper_insert *i,operand *o)
410 {
411 unsigned char v = o->extval[0];
412
413 *(d+1) |= ((v&1) ^ 1) << 7;
414 *(d+3) |= (v&2) << 3;
415 }
416
insert_ammx(unsigned char * d,struct oper_insert * i,operand * o)417 static void insert_ammx(unsigned char *d,struct oper_insert *i,operand *o)
418 {
419 unsigned char v = o->extval[0];
420
421 write_val(d,i->pos,i->size,v&15,0);
422 write_val(d,15-(i->flags&15),1,(v&16)!=0,0);
423 }
424
425 /* place to put an operand */
426 enum {
427 NOP=0,NEA,SEA,MEA,BEA,KEA,REA,EAM,BRA,DBR,RHI,RLO,RL4,R2H,R2M,R2L,R2P,
428 FPN,FPM,FMD,C2H,A2M,A2L,AXA,AXB,AXD,AX0,CS1,CS2,CS3,MDL,DVL,TBL,FPS,FPC,
429 RMM,RMW,RMY,RMX,ACX,ACR,DL8,DL4,D3Q,DL3,CAC,D16,S16,D2R,ELC,EL8,E8R,
430 EL3,EL4,EM3,EM4,EH3,BAX,FCR,F13,M3Q,MSF,ACW,AHI,ALO,LIN
431 };
432
433 struct oper_insert insert_info[] = {
434 /* NOP do nothing for this operand (usually a special reg.) */
435 M_nop,0,0,0,0,
436
437 /* NEA don't store effective address, but extension words */
438 M_noea,0,0,0,0,
439
440 /* SEA standard effective address */
441 M_ea,0,0,0,0,
442
443 /* MEA high effective address for MOVE */
444 M_high_ea,0,0,0,0,
445
446 /* BEA std. EA including bitfield offset/width */
447 M_bfea,0,0,0,0,
448
449 /* KEA std. EA including K-factor */
450 M_kfea,0,0,0,0,
451
452 /* REA store only register-part of effective address */
453 M_ea,0,0,IIF_NOMODE,0,
454
455 /* EAM standard effective address with MAC MASK-flag in bit 5 of 2nd word */
456 M_ea,0,5,IIF_MASK,0,
457
458 /* BRA pc-relative branch to label */
459 M_branch,0,0,IIF_BCC,0,
460
461 /* DBR DBcc, FBcc or PBcc branch to label */
462 M_branch,0,0,0,0,
463
464 /* RHI register 3 bits in bits 11-9 */
465 M_reg,3,4,0,0,
466
467 /* RLO register 3 bits in bits 2-0 */
468 M_reg,3,13,0,0,
469
470 /* RL4 register 4 bits in bits 3-0 */
471 M_reg,4,12,0,0,
472
473 /* R2H register 3 bits in 2nd word bits 14-12 */
474 M_reg,3,17,0,0,
475
476 /* R2M register 3 bits in 2nd word bits 8-6 */
477 M_reg,3,23,0,0,
478
479 /* R2L register 3 bits in 2nd word bits 2-0 */
480 M_reg,3,29,0,0,
481
482 /* R2P register 3 bits in 2nd word bits 7-5 */
483 M_reg,3,24,0,0,
484
485 /* FPN register 3 bits in 2nd word bits 9-7 (FPn) */
486 M_reg,3,22,0,0,
487
488 /* FPM register 3 bits in 2nd word bits 12-10 (FPm) */
489 M_reg,3,19,0,0,
490
491 /* FMD register 3 bits in 2nd word bits 6-4 (FMOVE dynamic) */
492 M_reg,3,25,0,0,
493
494 /* C2H register 4 bits in 2nd word bits 15-12 (cmp2,chk2,moves) */
495 M_reg,4,16,0,0,
496
497 /* A2M register 4 bits in 2nd word bits 11-8 (Apollo AMMX) */
498 M_reg,4,20,0,0,
499
500 /* A2L register 4 bits in 2nd word bits 3-0 (Apollo AMMX) */
501 M_reg,4,28,0,0,
502
503 /* AXA vector register field A (Apollo AMMX) */
504 M_func,4,28,IIF_A|IIF_ABSVAL,insert_ammx,
505
506 /* AXB vector register field B (Apollo AMMX) */
507 M_func,4,16,IIF_B|IIF_ABSVAL,insert_ammx,
508
509 /* AXD vector register field D (Apollo AMMX) */
510 M_func,4,20,IIF_D|IIF_ABSVAL,insert_ammx,
511
512 /* AX0 vector register field A in first word (Apollo AMMX) */
513 M_func,4,12,IIF_A|IIF_ABSVAL,insert_ammx,
514
515 /* CS1 register 3 bits for CAS2 bits 2-0 */
516 M_func,3,29,0,insert_cas2,
517
518 /* CS2 register 3 bits for CAS2 bits 8-6 */
519 M_func,3,23,0,insert_cas2,
520
521 /* CS3 register 4 bits for CAS2 (CAS2) bits 15-12 */
522 M_func,4,16,0,insert_cas2,
523
524 /* MDL insert 4 bit reg. Dq/Dl into 2nd word bits 15-12/3-0 */
525 M_func,0,0,0,insert_muldivl,
526
527 /* DVL 4 bit Dq to 2nd word bits 15-12, Dr to bits 3-0 */
528 M_func,0,0,0,insert_divl,
529
530 /* TBL 3 bit Dym to 1st w. bits 2-0, Dyn to 2nd w. 2-0 */
531 M_func,0,0,0,insert_tbl,
532
533 /* FPS 3 bit FPn to 2nd word bits 12-10 (FPm) and 9-7 (FPn) */
534 M_func,0,0,0,insert_fp,
535
536 /* FPC 3 bit FPc to 2nd word bits 2-0, FPs to bits 9-7 */
537 M_func,0,0,0,insert_fpcs,
538
539 /* RMM register 4 bits in bits 3-0, MAC U/L flag in bit 6 of 2nd word */
540 M_func,0x40,12,0,insert_macreg,
541
542 /* RMW register 4 bits in bits 6,11-9, MAC U/L flag in bit 7 of 2nd word */
543 M_func,0x80,4,0,insert_macreg,
544
545 /* RMY register 4 bits in 2nd word bits 3-0, MAC U/L flag in bit 6 */
546 M_func,0x40,28,0,insert_macreg,
547
548 /* RMX register 4 bits in 2nd word bits 15-12, MAC U/L flag in bit 7 */
549 M_func,0x80,16,0,insert_macreg,
550
551 /* ACX 2 bits ACC: MSB in bit 4 of 2nd word, LSB in bit 7 of first word */
552 M_func,0,0,IIF_ABSVAL,insert_accx,
553
554 /* ACR 2 bits ACC: MSB in bit 4 of 2nd word, reversed LSB in bit 7 of first */
555 M_func,0,0,IIF_ABSVAL,insert_accx_rev,
556
557 /* DL8 8-bit data in lo-byte */
558 M_val0,8,8,IIF_SIGNED,0,
559
560 /* DL4 4-bit value in bits 3-0 */
561 M_val0,4,12,0,0,
562
563 /* D3Q addq/subq 3-bit quick data in bits 11-9 */
564 M_val0,3,4,IIF_MASK,0,
565
566 /* DL3 3-bit value in bits 2-0 */
567 M_val0,3,13,0,0,
568
569 /* CAC 2-bit cache field in bits 7-6 */
570 M_val0,2,8,0,0,
571
572 /* D16 16-bit data in 2nd word */
573 M_val0,16,16,0,0,
574
575 /* S16 signed 16-bit data in 2nd word */
576 M_val0,16,16,IIF_SIGNED,0,
577
578 /* D2R 16-bit reversed data in 2nd word (movem predec.) */
579 M_val0,16,16,IIF_REVERSE,0,
580
581 /* ELC 12-bit value in bits 11-0 of 2nd word */
582 M_val0,12,20,0,0,
583
584 /* EL8 8-bit data in lo-byte of extension word (2nd word) */
585 M_val0,8,24,0,0,
586
587 /* E8R 8-bit reversed data in lo-byte of 2nd word (fmovem) */
588 M_val0,8,24,IIF_REVERSE,0,
589
590 /* EL3 3-bit value in bits 2-0 of 2nd word */
591 M_val0,3,29,0,0,
592
593 /* EL4 4-bit value in bits 3-0 of 2nd word */
594 M_val0,4,28,0,0,
595
596 /* EM3 3-bit value in bits 7-5 of 2nd word */
597 M_val0,3,24,0,0,
598
599 /* EM4 4-bit value in bits 8-5 of 2nd word */
600 M_val0,4,23,0,0,
601
602 /* EH3 3-bit value in bits 12-10 of 2nd word */
603 M_val0,3,19,0,0,
604
605 /* BAX 3-bit number of BAC/BAD reg. in bits 4-2 of 2nd word */
606 M_val0,3,27,0,0,
607
608 /* FCR 7-bit ROM offset in bits 6-0 of 2nd word (FMOVECR) */
609 M_val0,7,25,0,0,
610
611 /* F13 13-bit special register mask in bits 12-0 of 2nd word (FMOVEM) */
612 M_val0,13,19,0,0,
613
614 /* M3Q mov3q 3-bit quick data in bits 11-9, -1 is written as 0 */
615 M_val0,3,4,IIF_3Q,0,
616
617 /* MSF 2-bit MAC scale factor in bits 10-9 of 2nd word */
618 M_val0,2,21,0,0,
619
620 /* ACW 2-bit ACC in bits 3-2 of 2nd word */
621 M_val0,2,28,0,0,
622
623 /* AHI 2-bit ACC in bits 10-9 */
624 M_val0,2,5,0,0,
625
626 /* ALO 2-bit ACC in bits 1-0 */
627 M_val0,2,14,0,0,
628
629 /* LIN 12-bit value in bits 0-11 (LINE-A, LINE-F) */
630 M_val0,12,4,0,0,
631 };
632