Searched refs:REG_FIQSRC (Results 1 – 9 of 9) sorted by relevance
24 #define REG_FIQSRC 0x70 macro177 } else if (offset >= REG_IRQSRC && offset < REG_FIQSRC) { in bcm2836_control_read()179 } else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) { in bcm2836_control_read()180 return s->fiqsrc[(offset - REG_FIQSRC) >> 2]; in bcm2836_control_read()
32 #define REG_FIQSRC 0x70 macro260 } else if (offset >= REG_IRQSRC && offset < REG_FIQSRC) { in bcm2836_control_read()262 } else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) { in bcm2836_control_read()263 return s->fiqsrc[(offset - REG_FIQSRC) >> 2]; in bcm2836_control_read()
34 #define REG_FIQSRC 0x70 macro262 } else if (offset >= REG_IRQSRC && offset < REG_FIQSRC) { in bcm2836_control_read()264 } else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) { in bcm2836_control_read()265 return s->fiqsrc[(offset - REG_FIQSRC) >> 2]; in bcm2836_control_read()
34 #define REG_FIQSRC 0x70262 } else if (offset >= REG_IRQSRC && offset < REG_FIQSRC) {264 } else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) {265 return s->fiqsrc[(offset - REG_FIQSRC) >> 2];