/dports/lang/v8/v8-9.6.180.12/src/diagnostics/x64/ |
H A D | disasm-x64.cc | 53 {0x03, REG_OPER_OP_ORDER, "add"}, 57 {0x0B, REG_OPER_OP_ORDER, "or"}, 61 {0x13, REG_OPER_OP_ORDER, "adc"}, 65 {0x1B, REG_OPER_OP_ORDER, "sbb"}, 69 {0x23, REG_OPER_OP_ORDER, "and"}, 73 {0x2B, REG_OPER_OP_ORDER, "sub"}, 77 {0x33, REG_OPER_OP_ORDER, "xor"}, 81 {0x3B, REG_OPER_OP_ORDER, "cmp"}, 90 {0x8B, REG_OPER_OP_ORDER, "mov"}, 91 {0x8D, REG_OPER_OP_ORDER, "lea"}, [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/diagnostics/x64/ |
H A D | disasm-x64.cc | 52 {0x03, REG_OPER_OP_ORDER, "add"}, 56 {0x0B, REG_OPER_OP_ORDER, "or"}, 60 {0x13, REG_OPER_OP_ORDER, "adc"}, 64 {0x1B, REG_OPER_OP_ORDER, "sbb"}, 68 {0x23, REG_OPER_OP_ORDER, "and"}, 72 {0x2B, REG_OPER_OP_ORDER, "sub"}, 76 {0x33, REG_OPER_OP_ORDER, "xor"}, 80 {0x3B, REG_OPER_OP_ORDER, "cmp"}, 89 {0x8B, REG_OPER_OP_ORDER, "mov"}, 90 {0x8D, REG_OPER_OP_ORDER, "lea"}, [all …]
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/dports/www/node10/node-v10.24.1/deps/v8/src/x64/ |
H A D | disasm-x64.cc | 45 { 0x03, REG_OPER_OP_ORDER, "add" }, 49 { 0x0B, REG_OPER_OP_ORDER, "or" }, 53 { 0x13, REG_OPER_OP_ORDER, "adc" }, 57 { 0x1B, REG_OPER_OP_ORDER, "sbb" }, 61 { 0x23, REG_OPER_OP_ORDER, "and" }, 65 { 0x2B, REG_OPER_OP_ORDER, "sub" }, 69 { 0x33, REG_OPER_OP_ORDER, "xor" }, 73 { 0x3B, REG_OPER_OP_ORDER, "cmp" }, 82 { 0x8B, REG_OPER_OP_ORDER, "mov" }, 83 { 0x8D, REG_OPER_OP_ORDER, "lea" }, [all …]
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/dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/diagnostics/x64/ |
H A D | disasm-x64.cc | 47 {0x03, REG_OPER_OP_ORDER, "add"}, 51 {0x0B, REG_OPER_OP_ORDER, "or"}, 55 {0x13, REG_OPER_OP_ORDER, "adc"}, 59 {0x1B, REG_OPER_OP_ORDER, "sbb"}, 63 {0x23, REG_OPER_OP_ORDER, "and"}, 67 {0x2B, REG_OPER_OP_ORDER, "sub"}, 71 {0x33, REG_OPER_OP_ORDER, "xor"}, 75 {0x3B, REG_OPER_OP_ORDER, "cmp"}, 84 {0x8B, REG_OPER_OP_ORDER, "mov"}, 85 {0x8D, REG_OPER_OP_ORDER, "lea"}, [all …]
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/dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/diagnostics/ia32/ |
H A D | disasm-ia32.cc | 30 {0x01, "add", OPER_REG_OP_ORDER}, {0x03, "add", REG_OPER_OP_ORDER}, 31 {0x09, "or", OPER_REG_OP_ORDER}, {0x0B, "or", REG_OPER_OP_ORDER}, 32 {0x13, "adc", REG_OPER_OP_ORDER}, {0x1B, "sbb", REG_OPER_OP_ORDER}, 33 {0x21, "and", OPER_REG_OP_ORDER}, {0x23, "and", REG_OPER_OP_ORDER}, 38 {0x3B, "cmp", REG_OPER_OP_ORDER}, {0x84, "test_b", REG_OPER_OP_ORDER}, 39 {0x85, "test", REG_OPER_OP_ORDER}, {0x86, "xchg_b", REG_OPER_OP_ORDER}, 40 {0x87, "xchg", REG_OPER_OP_ORDER}, {0x8A, "mov_b", REG_OPER_OP_ORDER}, 41 {0x8B, "mov", REG_OPER_OP_ORDER}, {0x8D, "lea", REG_OPER_OP_ORDER}, 479 case REG_OPER_OP_ORDER: { in PrintOperands() 1729 data += PrintOperands("imul", REG_OPER_OP_ORDER, data); in InstructionDecode() [all …]
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/dports/www/node10/node-v10.24.1/deps/v8/src/ia32/ |
H A D | disasm-ia32.cc | 19 REG_OPER_OP_ORDER, enumerator 34 {0x01, "add", OPER_REG_OP_ORDER}, {0x03, "add", REG_OPER_OP_ORDER}, 35 {0x09, "or", OPER_REG_OP_ORDER}, {0x0B, "or", REG_OPER_OP_ORDER}, 36 {0x13, "adc", REG_OPER_OP_ORDER}, {0x1B, "sbb", REG_OPER_OP_ORDER}, 42 {0x3B, "cmp", REG_OPER_OP_ORDER}, {0x84, "test_b", REG_OPER_OP_ORDER}, 43 {0x85, "test", REG_OPER_OP_ORDER}, {0x86, "xchg_b", REG_OPER_OP_ORDER}, 44 {0x87, "xchg", REG_OPER_OP_ORDER}, {0x8A, "mov_b", REG_OPER_OP_ORDER}, 45 {0x8B, "mov", REG_OPER_OP_ORDER}, {0x8D, "lea", REG_OPER_OP_ORDER}, 528 case REG_OPER_OP_ORDER: { in PrintOperands() 1593 data += PrintOperands("imul", REG_OPER_OP_ORDER, data); in InstructionDecode() [all …]
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/dports/lang/v8/v8-9.6.180.12/src/diagnostics/ia32/ |
H A D | disasm-ia32.cc | 30 {0x01, "add", OPER_REG_OP_ORDER}, {0x03, "add", REG_OPER_OP_ORDER}, 31 {0x09, "or", OPER_REG_OP_ORDER}, {0x0B, "or", REG_OPER_OP_ORDER}, 32 {0x13, "adc", REG_OPER_OP_ORDER}, {0x1B, "sbb", REG_OPER_OP_ORDER}, 33 {0x21, "and", OPER_REG_OP_ORDER}, {0x23, "and", REG_OPER_OP_ORDER}, 38 {0x3B, "cmp", REG_OPER_OP_ORDER}, {0x84, "test_b", REG_OPER_OP_ORDER}, 39 {0x85, "test", REG_OPER_OP_ORDER}, {0x86, "xchg_b", REG_OPER_OP_ORDER}, 40 {0x87, "xchg", REG_OPER_OP_ORDER}, {0x8A, "mov_b", REG_OPER_OP_ORDER}, 41 {0x8B, "mov", REG_OPER_OP_ORDER}, {0x8D, "lea", REG_OPER_OP_ORDER}, 480 case REG_OPER_OP_ORDER: { in PrintOperands() 1880 data += PrintOperands("imul", REG_OPER_OP_ORDER, data); in InstructionDecode() [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/diagnostics/ia32/ |
H A D | disasm-ia32.cc | 30 {0x01, "add", OPER_REG_OP_ORDER}, {0x03, "add", REG_OPER_OP_ORDER}, 31 {0x09, "or", OPER_REG_OP_ORDER}, {0x0B, "or", REG_OPER_OP_ORDER}, 32 {0x13, "adc", REG_OPER_OP_ORDER}, {0x1B, "sbb", REG_OPER_OP_ORDER}, 33 {0x21, "and", OPER_REG_OP_ORDER}, {0x23, "and", REG_OPER_OP_ORDER}, 38 {0x3B, "cmp", REG_OPER_OP_ORDER}, {0x84, "test_b", REG_OPER_OP_ORDER}, 39 {0x85, "test", REG_OPER_OP_ORDER}, {0x86, "xchg_b", REG_OPER_OP_ORDER}, 40 {0x87, "xchg", REG_OPER_OP_ORDER}, {0x8A, "mov_b", REG_OPER_OP_ORDER}, 41 {0x8B, "mov", REG_OPER_OP_ORDER}, {0x8D, "lea", REG_OPER_OP_ORDER}, 479 case REG_OPER_OP_ORDER: { in PrintOperands() 1759 data += PrintOperands("imul", REG_OPER_OP_ORDER, data); in InstructionDecode() [all …]
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