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Searched refs:REG_STATUS (Results 1 – 25 of 342) sorted by relevance

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/dports/games/libretro-mame2003/mame2003-libretro-4358db4/src/machine/
H A Dam53cf96.c34 REG_STATUS, // read = status, write = destination SCSI ID (4) enumerator
64 if (reg == REG_STATUS) in READ32_HANDLER()
66 scsi_regs[REG_STATUS] &= ~0x7; in READ32_HANDLER()
67 scsi_regs[REG_STATUS] |= states[xfer_state]; in READ32_HANDLER()
80 scsi_regs[REG_STATUS] &= ~0x80; // clear IRQ flag in READ32_HANDLER()
106 scsi_regs[REG_STATUS] &= ~0x10; // clear CTZ bit in WRITE32_HANDLER()
133 scsi_regs[REG_STATUS] |= 0x80; // indicate IRQ in WRITE32_HANDLER()
139 scsi_regs[REG_STATUS] |= 0x80; // indicate IRQ in WRITE32_HANDLER()
179 scsi_regs[REG_STATUS] |= 0x80; // indicate IRQ in WRITE32_HANDLER()
186 if (reg != REG_STATUS && reg != REG_INTSTATE && reg != REG_IRQSTATE && reg != REG_FIFOSTATE) in WRITE32_HANDLER()
[all …]
/dports/emulators/mess/mame-mame0226/src/devices/machine/
H A Dam53cf96.cpp22 if (offset == REG_STATUS) in read()
24 scsi_regs[REG_STATUS] &= ~0x7; in read()
25 scsi_regs[REG_STATUS] |= states[xfer_state]; in read()
44 scsi_regs[REG_STATUS] &= ~0x80; // clear IRQ flag in read()
53 scsi_regs[REG_STATUS] |= 0x80; // indicate IRQ in device_timer()
62 if (offset == REG_STATUS) in write()
69 scsi_regs[REG_STATUS] &= ~0x10; // clear CTZ bit in write()
142 …if (offset != REG_STATUS && offset != REG_INTSTATE && offset != REG_IRQSTATE && offset != REG_FIFO… in write()
178 scsi_regs[REG_STATUS] |= 0x10; // indicate DMA finished in dma_read_data()
188 scsi_regs[REG_STATUS] |= 0x10; // indicate DMA finished in dma_write_data()
/dports/emulators/mame/mame-mame0226/src/devices/machine/
H A Dam53cf96.cpp22 if (offset == REG_STATUS) in read()
24 scsi_regs[REG_STATUS] &= ~0x7; in read()
25 scsi_regs[REG_STATUS] |= states[xfer_state]; in read()
44 scsi_regs[REG_STATUS] &= ~0x80; // clear IRQ flag in read()
53 scsi_regs[REG_STATUS] |= 0x80; // indicate IRQ in device_timer()
62 if (offset == REG_STATUS) in write()
69 scsi_regs[REG_STATUS] &= ~0x10; // clear CTZ bit in write()
142 …if (offset != REG_STATUS && offset != REG_INTSTATE && offset != REG_IRQSTATE && offset != REG_FIFO… in write()
178 scsi_regs[REG_STATUS] |= 0x10; // indicate DMA finished in dma_read_data()
188 scsi_regs[REG_STATUS] |= 0x10; // indicate DMA finished in dma_write_data()
/dports/games/libretro-mame2003_plus/mame2003-plus-libretro-17e9889/src/machine/
H A Dam53cf96.c34 REG_STATUS, /* read = status, write = destination SCSI ID (4)*/ enumerator
64 if (reg == REG_STATUS) in READ32_HANDLER()
66 scsi_regs[REG_STATUS] &= ~0x7; in READ32_HANDLER()
67 scsi_regs[REG_STATUS] |= states[xfer_state]; in READ32_HANDLER()
80 scsi_regs[REG_STATUS] &= ~0x80; /* clear IRQ flag*/ in READ32_HANDLER()
106 scsi_regs[REG_STATUS] &= ~0x10; /* clear CTZ bit*/ in WRITE32_HANDLER()
133 scsi_regs[REG_STATUS] |= 0x80; /* indicate IRQ*/ in WRITE32_HANDLER()
139 scsi_regs[REG_STATUS] |= 0x80; /* indicate IRQ*/ in WRITE32_HANDLER()
179 scsi_regs[REG_STATUS] |= 0x80; /* indicate IRQ*/ in WRITE32_HANDLER()
186 if (reg != REG_STATUS && reg != REG_INTSTATE && reg != REG_IRQSTATE && reg != REG_FIFOSTATE) in WRITE32_HANDLER()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/opensbi/lib/utils/serial/
H A Dshakti-uart.c14 #define REG_STATUS 0x0C macro
25 while((readw(uart_base + REG_STATUS) & 0x2) == 0); in shakti_uart_putc()
31 u16 status = readw(uart_base + REG_STATUS); in shakti_uart_getc()
/dports/emulators/qemu60/qemu-6.0.0/roms/opensbi/lib/utils/serial/
H A Dshakti-uart.c14 #define REG_STATUS 0x0C macro
28 while((readw(uart_base + REG_STATUS) & UART_TX_FULL)) in shakti_uart_putc()
35 u16 status = readw(uart_base + REG_STATUS); in shakti_uart_getc()
/dports/sysutils/opensbi/opensbi-0.9/lib/utils/serial/
H A Dshakti-uart.c14 #define REG_STATUS 0x0C macro
28 while((readw(uart_base + REG_STATUS) & UART_TX_FULL)) in shakti_uart_putc()
35 u16 status = readw(uart_base + REG_STATUS); in shakti_uart_getc()
/dports/emulators/qemu/qemu-6.2.0/roms/opensbi/lib/utils/serial/
H A Dshakti-uart.c14 #define REG_STATUS 0x0C macro
28 while((readw(uart_base + REG_STATUS) & UART_TX_FULL)) in shakti_uart_putc()
35 u16 status = readw(uart_base + REG_STATUS); in shakti_uart_getc()
/dports/games/libretro-mame2000/mame2000-libretro-e364a15/src/vidhrdw/
H A Dtms34061.c30 #define REG_STATUS 13 macro
61 regs[REG_STATUS] = 0x00; in TMS34061_start()
127 regs[REG_STATUS] |= 0x0001; in TMS34061_intcallback()
156 case REG_STATUS: in READ_HANDLER()
/dports/graphics/sane-backends/sane-backends-1.0.32/backend/
H A Du12-motor.c180 if( !(u12io_DataFromRegister( dev, REG_STATUS ) & _FLAG_PAPER)) { in u12motor_ToHomePosition()
187 if( u12io_DataFromRegister( dev, REG_STATUS ) & _FLAG_PAPER) in u12motor_ToHomePosition()
251 if( u12io_DataFromRegister( dev, REG_STATUS ) & _FLAG_PAPER ) in u12motor_BackToHomeSensor()
282 if(!(u12io_DataFromRegister( dev, REG_STATUS ) & _FLAG_PAPER)) { in u12motor_ModuleToHome()
408 if( !(u12io_DataFromRegister( dev, REG_STATUS ) & _FLAG_PAPER)) in u12motor_ForceToLeaveHomePos()
H A Du12-if.c119 if( !(u12io_DataFromRegister( dev, REG_STATUS ) & _FLAG_PAPER)) { in u12_initDev()
125 if( u12io_DataFromRegister( dev, REG_STATUS ) & _FLAG_PAPER) { in u12_initDev()
155 if( !(u12io_DataFromRegister( dev, REG_STATUS ) & _FLAG_PAPER)) { in u12if_shutdown()
161 if( u12io_DataFromRegister( dev, REG_STATUS ) & _FLAG_PAPER) { in u12if_shutdown()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/seeq/
H A Dether3.c122 while ((ether3_inw(REG_STATUS) & STAT_FIFOEMPTY) == 0) { in ether3_setbuffer()
328 while (ether3_inw(REG_STATUS) & (STAT_RXON|STAT_TXON)) in ether3_init_for_open()
422 while (ether3_inw(REG_STATUS) & (STAT_RXON|STAT_TXON)) in ether3_close()
462 ether3_inw(REG_STATUS), ether3_inw(REG_CONFIG1), ether3_inw(REG_CONFIG2)); in ether3_timeout()
529 if (!(ether3_inw(REG_STATUS) & STAT_TXON)) { in ether3_sendpacket()
557 status = ether3_inw(REG_STATUS); in ether3_interrupt()
673 if (!(ether3_inw(REG_STATUS) & STAT_RXON)) { in ether3_rx()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/seeq/
H A Dether3.c122 while ((ether3_inw(REG_STATUS) & STAT_FIFOEMPTY) == 0) { in ether3_setbuffer()
328 while (ether3_inw(REG_STATUS) & (STAT_RXON|STAT_TXON)) in ether3_init_for_open()
422 while (ether3_inw(REG_STATUS) & (STAT_RXON|STAT_TXON)) in ether3_close()
462 ether3_inw(REG_STATUS), ether3_inw(REG_CONFIG1), ether3_inw(REG_CONFIG2)); in ether3_timeout()
529 if (!(ether3_inw(REG_STATUS) & STAT_TXON)) { in ether3_sendpacket()
557 status = ether3_inw(REG_STATUS); in ether3_interrupt()
673 if (!(ether3_inw(REG_STATUS) & STAT_RXON)) { in ether3_rx()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/seeq/
H A Dether3.c122 while ((ether3_inw(REG_STATUS) & STAT_FIFOEMPTY) == 0) { in ether3_setbuffer()
328 while (ether3_inw(REG_STATUS) & (STAT_RXON|STAT_TXON)) in ether3_init_for_open()
422 while (ether3_inw(REG_STATUS) & (STAT_RXON|STAT_TXON)) in ether3_close()
462 ether3_inw(REG_STATUS), ether3_inw(REG_CONFIG1), ether3_inw(REG_CONFIG2)); in ether3_timeout()
529 if (!(ether3_inw(REG_STATUS) & STAT_TXON)) { in ether3_sendpacket()
557 status = ether3_inw(REG_STATUS); in ether3_interrupt()
673 if (!(ether3_inw(REG_STATUS) & STAT_RXON)) { in ether3_rx()
/dports/games/openbor3482/openbor-2c1ecd7/engine/psp/exception/
H A Dexception_asm.S56 #define REG_STATUS (REG_GPR_31 + 4) macro
57 #define REG_LO (REG_STATUS + 4)
157 sw $v1, REG_STATUS($v0)
/dports/games/openbor3979/openbor-2bcf25b/engine/psp/exception/
H A Dexception_asm.S56 #define REG_STATUS (REG_GPR_31 + 4) macro
57 #define REG_LO (REG_STATUS + 4)
157 sw $v1, REG_STATUS($v0)
/dports/games/openbor3711/openbor-6ec17fa/engine/psp/exception/
H A Dexception_asm.S56 #define REG_STATUS (REG_GPR_31 + 4) macro
57 #define REG_LO (REG_STATUS + 4)
157 sw $v1, REG_STATUS($v0)
/dports/games/openbor4432/openbor-ba1eb4f/engine/psp/exception/
H A Dexception_asm.S56 #define REG_STATUS (REG_GPR_31 + 4) macro
57 #define REG_LO (REG_STATUS + 4)
157 sw $v1, REG_STATUS($v0)
/dports/games/openbor/openbor-3caaddd5/engine/psp/exception/
H A Dexception_asm.S56 #define REG_STATUS (REG_GPR_31 + 4) macro
57 #define REG_LO (REG_STATUS + 4)
157 sw $v1, REG_STATUS($v0)
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/media/spi/
H A Dgs1662.c26 #define REG_STATUS 0x04 macro
310 gs_read_register(gs->pdev, REG_STATUS, &reg_value); in gs_query_dv_timings()
383 ret = gs_read_register(gs->pdev, REG_STATUS, &reg_value); in gs_g_input_status()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/media/dvb-frontends/
H A Dlgs8gl5.c38 #define REG_STATUS 0xa4 macro
205 val = lgs8gl5_read_reg(state, REG_STATUS); in lgs8gl5_start_demod()
244 u8 flags = lgs8gl5_read_reg(state, REG_STATUS); in lgs8gl5_read_status()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/media/dvb-frontends/
H A Dlgs8gl5.c38 #define REG_STATUS 0xa4 macro
205 val = lgs8gl5_read_reg(state, REG_STATUS); in lgs8gl5_start_demod()
244 u8 flags = lgs8gl5_read_reg(state, REG_STATUS); in lgs8gl5_read_status()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/media/spi/
H A Dgs1662.c26 #define REG_STATUS 0x04 macro
310 gs_read_register(gs->pdev, REG_STATUS, &reg_value); in gs_query_dv_timings()
383 ret = gs_read_register(gs->pdev, REG_STATUS, &reg_value); in gs_g_input_status()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/media/spi/
H A Dgs1662.c26 #define REG_STATUS 0x04 macro
310 gs_read_register(gs->pdev, REG_STATUS, &reg_value); in gs_query_dv_timings()
383 ret = gs_read_register(gs->pdev, REG_STATUS, &reg_value); in gs_g_input_status()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/media/dvb-frontends/
H A Dlgs8gl5.c38 #define REG_STATUS 0xa4 macro
205 val = lgs8gl5_read_reg(state, REG_STATUS); in lgs8gl5_start_demod()
244 u8 flags = lgs8gl5_read_reg(state, REG_STATUS); in lgs8gl5_read_status()

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