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Searched refs:RELOAD_REG_GPR (Results 1 – 25 of 26) sorted by relevance

12

/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c3056 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3617 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3621 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3625 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3629 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3633 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3637 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3641 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3645 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3649 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/rs6000/
H A Drs6000.c3056 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3617 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3621 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3625 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3629 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3633 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3637 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3641 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3645 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3649 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c3056 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3617 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3621 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3625 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3629 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3633 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3637 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3641 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3645 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3649 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c3056 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3617 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3621 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3625 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3629 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3633 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3637 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3641 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3645 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3649 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c3056 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3617 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3621 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3625 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3629 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3633 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3637 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3641 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3645 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3649 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/lang/gcc8/gcc-8.5.0/gcc/config/rs6000/
H A Drs6000.c3056 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3617 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3621 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3625 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3629 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3633 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3637 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3641 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3645 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3649 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/lang/gnat_util/gcc-6-20180516/gcc/config/rs6000/
H A Drs6000.c2900 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3453 { QImode, DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3457 { QImode, SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3461 { HImode, DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3465 { HImode, SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3469 { SImode, DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3473 { SImode, SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3477 { SFmode, DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3481 { SFmode, SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3485 { DImode, DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/rs6000/
H A Drs6000.c2900 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3453 { QImode, DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3457 { QImode, SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3461 { HImode, DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3465 { HImode, SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3469 { SImode, DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3473 { SImode, SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3477 { SFmode, DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3481 { SFmode, SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3485 { DImode, DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c3082 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3668 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3672 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3676 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3680 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3684 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3688 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3692 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3696 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3700 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c3082 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3668 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3672 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3676 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3680 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3684 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3688 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3692 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3696 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3700 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c3082 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3668 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3672 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3676 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3680 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3684 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3688 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3692 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3696 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3700 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c3082 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3668 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3672 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3676 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3680 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3684 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3688 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3692 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3696 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3700 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c3082 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3668 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3672 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3676 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3680 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3684 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3688 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3692 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3696 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3700 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/lang/gcc8/gcc-8.5.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c3082 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
3668 { E_QImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3672 { E_QImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3676 { E_HImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3680 { E_HImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3684 { E_SImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3688 { E_SImode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3692 { E_SFmode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3696 { E_SFmode, E_SImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
3700 { E_DImode, E_DImode, RELOAD_REG_GPR, in rs6000_init_hard_regno_mode_ok()
[all …]
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/rs6000/
H A Drs6000.c330 RELOAD_REG_GPR, /* General purpose registers. */ enumerator
340 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
2674 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) in rs6000_setup_reg_addr_masks()
2713 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
12221 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_memory()
12980 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_inner()
/dports/devel/avr-gcc/gcc-10.2.0/gcc/config/rs6000/
H A Drs6000.c328 RELOAD_REG_GPR, /* General purpose registers. */ enumerator
338 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
2644 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) in rs6000_setup_reg_addr_masks()
2683 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
11088 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_memory()
11847 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_inner()
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/rs6000/
H A Drs6000.c326 RELOAD_REG_GPR, /* General purpose registers. */ enumerator
336 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
2669 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) in rs6000_setup_reg_addr_masks()
2708 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
11841 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_memory()
12600 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_inner()
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/rs6000/
H A Drs6000.c328 RELOAD_REG_GPR, /* General purpose registers. */ enumerator
338 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
2650 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) in rs6000_setup_reg_addr_masks()
2689 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
11090 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_memory()
11849 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_inner()
/dports/lang/gcc11/gcc-11.2.0/gcc/config/rs6000/
H A Drs6000.c326 RELOAD_REG_GPR, /* General purpose registers. */ enumerator
336 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
2669 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) in rs6000_setup_reg_addr_masks()
2708 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
11837 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_memory()
12596 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_inner()
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/rs6000/
H A Drs6000.c326 RELOAD_REG_GPR, /* General purpose registers. */ enumerator
336 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
2669 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) in rs6000_setup_reg_addr_masks()
2708 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
11837 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_memory()
12596 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_inner()
/dports/lang/gcc10/gcc-10.3.0/gcc/config/rs6000/
H A Drs6000.c328 RELOAD_REG_GPR, /* General purpose registers. */ enumerator
338 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
2650 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) in rs6000_setup_reg_addr_masks()
2689 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
11090 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_memory()
11849 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_inner()
/dports/lang/gcc9/gcc-9.4.0/gcc/config/rs6000/
H A Drs6000.c489 RELOAD_REG_GPR, /* General purpose registers. */ enumerator
499 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
2909 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) in rs6000_setup_reg_addr_masks()
2948 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
7157 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR]; in rs6000_adjust_vec_address()
19319 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_memory()
20084 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_inner()
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/rs6000/
H A Drs6000.c489 RELOAD_REG_GPR, /* General purpose registers. */ enumerator
499 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
2909 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) in rs6000_setup_reg_addr_masks()
2948 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
7131 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR]; in rs6000_adjust_vec_address()
19111 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_memory()
19876 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_inner()
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/rs6000/
H A Drs6000.c489 RELOAD_REG_GPR, /* General purpose registers. */ enumerator
499 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
2909 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) in rs6000_setup_reg_addr_masks()
2948 && (rc == RELOAD_REG_GPR in rs6000_setup_reg_addr_masks()
7157 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR]; in rs6000_adjust_vec_address()
19319 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_memory()
20084 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; in rs6000_secondary_reload_inner()
/dports/lang/gcc48/gcc-4.8.5/gcc/config/rs6000/
H A Drs6000.c328 RELOAD_REG_GPR, /* General purpose registers. */ enumerator
338 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
2372 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) in rs6000_setup_reg_addr_masks()
2408 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)) in rs6000_setup_reg_addr_masks()

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