| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/rs6000/ |
| H A D | rs6000.c | 365 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
387 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2154 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2683 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
12243 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
12279 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
13010 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/devel/avr-gcc/gcc-10.2.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 363 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
385 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2125 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2653 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
11110 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
11146 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
11877 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/rs6000/ |
| H A D | rs6000.c | 361 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
383 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2149 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2678 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
11863 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
11899 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
12630 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/rs6000/ |
| H A D | rs6000.c | 363 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
385 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2128 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2659 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
11112 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
11148 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
11879 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gcc11/gcc-11.2.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 361 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
383 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2149 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2678 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
11859 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
11895 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
12626 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 361 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
383 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2149 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2678 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
11859 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
11895 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
12626 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gcc10/gcc-10.3.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 363 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
385 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2128 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2659 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
11112 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
11148 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
11879 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 527 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
559 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2372 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3026 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
19867 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
19903 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
20640 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gcc9/gcc-9.4.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 524 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
546 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2349 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2918 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
19341 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
19377 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
20114 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gnat_util/gcc-6-20180516/gcc/config/rs6000/ |
| H A D | rs6000.c | 456 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
488 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2227 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2870 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
19043 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
19079 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
19824 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 527 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
559 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2372 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3026 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
19724 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
19760 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
20497 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 527 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
559 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2372 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3026 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
19867 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
19903 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
20640 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 527 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
559 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2372 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3026 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
19867 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
19903 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
20640 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 527 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
559 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2372 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3026 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
19867 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
19903 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
20640 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 524 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
546 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2349 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2918 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
19133 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
19169 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
19906 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/rs6000/ |
| H A D | rs6000.c | 524 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
546 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2349 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2918 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
19341 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
19377 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
20114 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gcc8/gcc-8.5.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 527 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
559 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2372 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3026 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
19881 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
19917 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
20654 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/rs6000/ |
| H A D | rs6000.c | 456 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
488 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2227 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
2870 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
19043 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
19079 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
19824 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 477 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
509 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2389 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3052 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
21959 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
21995 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
22732 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 477 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
509 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2389 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3052 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
21959 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
21995 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
22732 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 477 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
509 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2389 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3052 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
21959 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
21995 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
22732 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 477 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
509 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2389 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3052 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
21959 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
21995 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
22732 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 477 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
509 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2389 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3052 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
21959 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
21995 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
22732 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gcc8/gcc-8.5.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 477 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
509 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
2389 if ((mask & RELOAD_REG_PRE_INCDEC) != 0) in rs6000_debug_addr_mask()
3052 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
21959 | RELOAD_REG_PRE_INCDEC in rs6000_secondary_reload_memory()
21995 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_memory()
22732 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0) in rs6000_secondary_reload_inner()
|
| /dports/lang/gcc48/gcc-4.8.5/gcc/config/rs6000/ |
| H A D | rs6000.c | 363 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ macro
383 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) in mode_supports_pre_incdec_p()
1893 (mask & RELOAD_REG_PRE_INCDEC) != 0 ? '+' : ' ', in rs6000_debug_print_mode()
2380 addr_mask |= RELOAD_REG_PRE_INCDEC; in rs6000_setup_reg_addr_masks()
|