Home
last modified time | relevance | path

Searched refs:RELOAD_REG_PRE_MODIFY (Results 1 – 25 of 46) sorted by relevance

12

/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/rs6000/
H A Drs6000.c366 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
395 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2159 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2691 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2696 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2702 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
12244 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
12297 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
13028 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/devel/avr-gcc/gcc-10.2.0/gcc/config/rs6000/
H A Drs6000.c364 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
393 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2130 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2661 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2666 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2672 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
11111 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
11164 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
11895 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/rs6000/
H A Drs6000.c362 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
391 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2154 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2686 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2691 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2697 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
11864 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
11917 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
12648 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/rs6000/
H A Drs6000.c364 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
393 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2133 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2667 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2672 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2678 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
11113 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
11166 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
11897 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gcc11/gcc-11.2.0/gcc/config/rs6000/
H A Drs6000.c362 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
391 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2154 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2686 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2691 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2697 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
11860 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
11913 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
12644 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/rs6000/
H A Drs6000.c362 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
391 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2154 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2686 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2691 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2697 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
11860 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
11913 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
12644 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gcc10/gcc-10.3.0/gcc/config/rs6000/
H A Drs6000.c364 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
393 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2133 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2667 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2672 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2678 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
11113 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
11166 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
11897 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c528 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
567 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2377 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3034 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3039 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3045 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
19868 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
19921 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
20655 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gcc9/gcc-9.4.0/gcc/config/rs6000/
H A Drs6000.c525 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
554 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2354 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2926 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2931 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2937 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
19342 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
19395 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
20132 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gnat_util/gcc-6-20180516/gcc/config/rs6000/
H A Drs6000.c457 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
496 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2232 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2878 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2883 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2889 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
19044 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
19097 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
19839 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/rs6000/
H A Drs6000.c528 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
567 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2377 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3034 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3039 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3045 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
19725 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
19778 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
20512 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c528 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
567 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2377 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3034 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3039 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3045 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
19868 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
19921 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
20655 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c528 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
567 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2377 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3034 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3039 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3045 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
19868 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
19921 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
20655 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c528 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
567 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2377 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3034 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3039 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3045 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
19868 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
19921 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
20655 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/rs6000/
H A Drs6000.c525 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
554 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2354 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2926 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2931 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2937 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
19134 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
19187 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
19924 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/rs6000/
H A Drs6000.c525 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
554 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2354 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2926 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2931 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2937 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
19342 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
19395 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
20132 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gcc8/gcc-8.5.0/gcc/config/rs6000/
H A Drs6000.c528 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
567 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2377 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3034 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3039 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3045 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
19882 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
19935 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
20669 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/rs6000/
H A Drs6000.c457 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
496 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2232 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
2878 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2883 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2889 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
19044 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
19097 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
19839 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c478 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
517 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2394 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3060 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3065 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3071 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
21960 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
22013 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
22747 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c478 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
517 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2394 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3060 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3065 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3071 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
21960 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
22013 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
22747 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c478 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
517 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2394 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3060 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3065 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3071 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
21960 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
22013 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
22747 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c478 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
517 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2394 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3060 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3065 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3071 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
21960 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
22013 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
22747 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c478 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
517 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2394 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3060 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3065 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3071 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
21960 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
22013 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
22747 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gcc8/gcc-8.5.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c478 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
517 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
2394 if ((mask & RELOAD_REG_PRE_MODIFY) != 0) in rs6000_debug_addr_mask()
3060 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3065 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
3071 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
21960 | RELOAD_REG_PRE_MODIFY); in rs6000_secondary_reload_memory()
22013 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_memory()
22747 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0) in rs6000_secondary_reload_inner()
/dports/lang/gcc48/gcc-4.8.5/gcc/config/rs6000/
H A Drs6000.c364 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ macro
391 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) in mode_supports_pre_modify_p()
1894 (mask & RELOAD_REG_PRE_MODIFY) != 0 ? '+' : ' '); in rs6000_debug_print_mode()
2388 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2393 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()
2399 addr_mask |= RELOAD_REG_PRE_MODIFY; in rs6000_setup_reg_addr_masks()

12