| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/rs6000/ |
| H A D | rs6000.c | 332 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
341 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2645 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
2716 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
2729 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2741 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2751 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
6880 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID)) in xxspltib_constant_p()
12227 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
12231 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/devel/avr-gcc/gcc-10.2.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 330 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
339 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2615 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
2686 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
2699 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2711 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2721 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
6204 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID)) in xxspltib_constant_p()
11094 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
11098 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/rs6000/ |
| H A D | rs6000.c | 328 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
337 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2640 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
2711 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
2724 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2736 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2746 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
6460 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID)) in xxspltib_constant_p()
11847 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
11851 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/rs6000/ |
| H A D | rs6000.c | 330 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
339 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2621 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
2692 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
2705 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2717 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2727 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
6223 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID)) in xxspltib_constant_p()
11096 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
11100 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/lang/gcc11/gcc-11.2.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 328 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
337 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2640 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
2711 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
2724 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2736 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2746 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
6456 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID)) in xxspltib_constant_p()
11843 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
11847 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 328 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
337 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2640 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
2711 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
2724 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2736 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2746 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
6456 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID)) in xxspltib_constant_p()
11843 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
11847 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/lang/gcc10/gcc-10.3.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 330 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
339 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2621 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
2692 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
2705 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2717 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2727 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
6223 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID)) in xxspltib_constant_p()
11096 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
11100 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 494 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
503 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2988 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3059 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
3072 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3078 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3677 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3679 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
19851 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
19855 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 494 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
503 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2988 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3059 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
3072 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3078 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3677 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3679 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
19708 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
19712 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 494 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
503 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2988 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3059 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
3072 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3078 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3677 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3679 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
19851 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
19855 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 494 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
503 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2988 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3059 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
3072 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3078 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3677 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3679 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
19851 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
19855 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 494 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
503 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2988 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3059 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
3072 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3078 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3677 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3679 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
19851 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
19855 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/lang/gcc8/gcc-8.5.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 494 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
503 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2988 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3059 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
3072 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3078 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3677 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3679 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
19865 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
19869 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 444 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
453 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
3019 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3085 || (rc == RELOAD_REG_VMX in rs6000_setup_reg_addr_masks()
3099 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3105 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3729 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3731 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
21943 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
21947 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 444 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
453 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
3019 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3085 || (rc == RELOAD_REG_VMX in rs6000_setup_reg_addr_masks()
3099 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3105 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3729 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3731 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
21943 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
21947 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 444 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
453 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
3019 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3085 || (rc == RELOAD_REG_VMX in rs6000_setup_reg_addr_masks()
3099 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3105 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3729 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3731 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
21943 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
21947 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 444 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
453 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
3019 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3085 || (rc == RELOAD_REG_VMX in rs6000_setup_reg_addr_masks()
3099 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3105 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3729 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3731 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
21943 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
21947 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 444 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
453 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
3019 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3085 || (rc == RELOAD_REG_VMX in rs6000_setup_reg_addr_masks()
3099 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3105 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3729 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3731 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
21943 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
21947 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/lang/gcc8/gcc-8.5.0/gcc/config/powerpcspe/ |
| H A D | powerpcspe.c | 444 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
453 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
3019 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
3085 || (rc == RELOAD_REG_VMX in rs6000_setup_reg_addr_masks()
3099 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
3105 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3729 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3731 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
21943 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
21947 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/lang/gcc9/gcc-9.4.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 491 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
500 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2880 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
2951 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
2964 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2970 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
6393 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID)) in xxspltib_constant_p()
7163 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX]; in rs6000_adjust_vec_address()
19325 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
19329 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
|
| /dports/lang/gnat_util/gcc-6-20180516/gcc/config/rs6000/ |
| H A D | rs6000.c | 423 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
432 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2903 || (rc == RELOAD_REG_VMX in rs6000_setup_reg_addr_masks()
2917 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2923 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3514 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3516 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
6532 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0) in xxspltib_constant_p()
19027 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
19031 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
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| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/rs6000/ |
| H A D | rs6000.c | 491 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
500 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2880 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
2951 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
2964 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2970 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
6378 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID)) in xxspltib_constant_p()
7137 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX]; in rs6000_adjust_vec_address()
19117 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
19121 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
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| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/rs6000/ |
| H A D | rs6000.c | 491 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
500 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2880 || rc == RELOAD_REG_VMX)); in rs6000_setup_reg_addr_masks()
2951 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) in rs6000_setup_reg_addr_masks()
2964 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2970 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
6393 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID)) in xxspltib_constant_p()
7163 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX]; in rs6000_adjust_vec_address()
19325 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
19329 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
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| /dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/rs6000/ |
| H A D | rs6000.c | 423 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
432 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
2903 || (rc == RELOAD_REG_VMX in rs6000_setup_reg_addr_masks()
2917 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) in rs6000_setup_reg_addr_masks()
2923 if (rc == RELOAD_REG_VMX && msize == 16 in rs6000_setup_reg_addr_masks()
3514 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
3516 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX] in rs6000_init_hard_regno_mode_ok()
6532 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0) in xxspltib_constant_p()
19027 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; in rs6000_secondary_reload_memory()
19031 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] in rs6000_secondary_reload_memory()
[all …]
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| /dports/lang/gcc48/gcc-4.8.5/gcc/config/rs6000/ |
| H A D | rs6000.c | 330 RELOAD_REG_VMX, /* Altivec (VMX) registers. */ enumerator
339 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
|