| /dports/cad/yosys/yosys-yosys-0.12/techlibs/ice40/tests/ |
| H A D | test_ffs.sh | 5 for RESET_EN in 0 1; do
8 pf="test_ffs_${CLKPOL}${ENABLE_EN}${RESET_EN}${RESET_VAL}${RESET_SYN}"
10 -e "s/RESET_EN = 0/RESET_EN = ${RESET_EN}/;" -e "s/RESET_VAL = 0/RESET_VAL = ${RESET_VAL}/;" \
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| H A D | test_ffs.v | 4 parameter [0:0] RESET_EN = 0; constant
13 wire gated_reset = R & RESET_EN;
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| /dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | rv740d.h | 61 #define RESET_EN (1 << 25) macro
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| H A D | rv740_dpm.c | 347 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN; in rv740_populate_smc_acpi_state()
349 mpll_dq_func_cntl_2 |= BYPASS | BIAS_GEN_PDNB | RESET_EN; in rv740_populate_smc_acpi_state()
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| H A D | rv770d.h | 134 #define RESET_EN (1 << 25) macro
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
| H A D | rv740d.h | 61 #define RESET_EN (1 << 25) macro
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| H A D | rv740_dpm.c | 345 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN; in rv740_populate_smc_acpi_state()
347 mpll_dq_func_cntl_2 |= BYPASS | BIAS_GEN_PDNB | RESET_EN; in rv740_populate_smc_acpi_state()
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
| H A D | rv740d.h | 61 #define RESET_EN (1 << 25) macro
|
| H A D | rv740_dpm.c | 345 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN; in rv740_populate_smc_acpi_state()
347 mpll_dq_func_cntl_2 |= BYPASS | BIAS_GEN_PDNB | RESET_EN; in rv740_populate_smc_acpi_state()
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
| H A D | rv740d.h | 61 #define RESET_EN (1 << 25) macro
|
| H A D | rv740_dpm.c | 345 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN; in rv740_populate_smc_acpi_state()
347 mpll_dq_func_cntl_2 |= BYPASS | BIAS_GEN_PDNB | RESET_EN; in rv740_populate_smc_acpi_state()
|
| H A D | rv770d.h | 134 #define RESET_EN (1 << 25) macro
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| /dports/sysutils/u-boot-utilite/u-boot-2015.07/board/esd/pmc440/ |
| H A D | pmc440.h | 83 #define RESET_EN (1 << 31) macro
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/ |
| H A D | fifo_4k_2clk_pctrl.vhd | 99 RESET_EN : OUT STD_LOGIC; port
393 RESET_EN <= reset_en_rd2;
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| H A D | fifo_4k_2clk_synth.vhd | 266 RESET_EN => reset_en,
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| H A D | fifo_4k_2clk_pkg.vhd | 178 RESET_EN : OUT STD_LOGIC; port in fifo_4k_2clk_pkg.fifo_4k_2clk_pctrl
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/ |
| H A D | fifo_short_2clk_pctrl.vhd | 99 RESET_EN : OUT STD_LOGIC; port
393 RESET_EN <= reset_en_rd2;
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| H A D | fifo_short_2clk_synth.vhd | 266 RESET_EN => reset_en,
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| H A D | fifo_short_2clk_pkg.vhd | 178 RESET_EN : OUT STD_LOGIC; port in fifo_short_2clk_pkg.fifo_short_2clk_pctrl
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/ |
| H A D | fifo_short_2clk_pctrl.vhd | 99 RESET_EN : OUT STD_LOGIC; port
393 RESET_EN <= reset_en_rd2;
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| H A D | fifo_short_2clk_synth.vhd | 266 RESET_EN => reset_en,
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| H A D | fifo_short_2clk_pkg.vhd | 178 RESET_EN : OUT STD_LOGIC; port in fifo_short_2clk_pkg.fifo_short_2clk_pctrl
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/ |
| H A D | fifo_4k_2clk_pctrl.vhd | 99 RESET_EN : OUT STD_LOGIC; port
393 RESET_EN <= reset_en_rd2;
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| H A D | fifo_4k_2clk_synth.vhd | 266 RESET_EN => reset_en,
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| H A D | fifo_4k_2clk_pkg.vhd | 178 RESET_EN : OUT STD_LOGIC; port in fifo_4k_2clk_pkg.fifo_4k_2clk_pctrl
|