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Searched refs:RES_2 (Results 1 – 25 of 128) sorted by relevance

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/dports/emulators/mess/mame-mame0226/src/mame/video/
H A Dtankbatt.cpp25 constexpr int RES_2 = 0x3f; // this is a guess in tankbatt_palette() local
36 int const r = bit1 * (RES_1 + (RES_2 * bit0)); in tankbatt_palette()
39 int const g = bit2 * (RES_1 + (RES_2 * bit0)); in tankbatt_palette()
42 int const b = bit3 * (RES_1 + (RES_2 * bit0)); in tankbatt_palette()
/dports/emulators/mame/mame-mame0226/src/mame/video/
H A Dtankbatt.cpp25 constexpr int RES_2 = 0x3f; // this is a guess in tankbatt_palette() local
36 int const r = bit1 * (RES_1 + (RES_2 * bit0)); in tankbatt_palette()
39 int const g = bit2 * (RES_1 + (RES_2 * bit0)); in tankbatt_palette()
42 int const b = bit3 * (RES_1 + (RES_2 * bit0)); in tankbatt_palette()
/dports/games/libretro-mame2000/mame2000-libretro-e364a15/src/vidhrdw/
H A Dtankbatt.c27 #define RES_2 0x3f /* this is a guess */ in tankbatt_vh_convert_color_prom() macro
48 if (bit1) *(palette) += RES_2 * bit0; in tankbatt_vh_convert_color_prom()
52 if (bit2) *(palette) += RES_2 * bit0; in tankbatt_vh_convert_color_prom()
56 if (bit3) *(palette) += RES_2 * bit0; in tankbatt_vh_convert_color_prom()
/dports/games/libretro-mame2003/mame2003-libretro-4358db4/src/vidhrdw/
H A Dtankbatt_vidhrdw.c29 #define RES_2 0x3f /* this is a guess */ in PALETTE_INIT() macro
48 if (bit1) r += RES_2 * bit0; in PALETTE_INIT()
52 if (bit2) g += RES_2 * bit0; in PALETTE_INIT()
56 if (bit3) b += RES_2 * bit0; in PALETTE_INIT()
/dports/games/libretro-mame2003_plus/mame2003-plus-libretro-17e9889/src/vidhrdw/
H A Dtankbatt_vidhrdw.c29 #define RES_2 0x3f /* this is a guess */ in PALETTE_INIT() macro
48 if (bit1) r += RES_2 * bit0; in PALETTE_INIT()
52 if (bit2) g += RES_2 * bit0; in PALETTE_INIT()
56 if (bit3) b += RES_2 * bit0; in PALETTE_INIT()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/ConstraintElimination/
H A Dassumes.ll23 ; CHECK-NEXT: ret i1 [[RES_2]]
71 ; CHECK-NEXT: ret i1 [[RES_2]]
120 ; CHECK-NEXT: ret i1 [[RES_2]]
166 ; CHECK-NEXT: ret i1 [[RES_2]]
193 ; CHECK-NEXT: ret i1 [[RES_2]]
240 ; CHECK-NEXT: ret i1 [[RES_2]]
274 ; CHECK-NEXT: ret i1 [[RES_2]]
308 ; CHECK-NEXT: ret i1 [[RES_2]]
339 ; CHECK-NEXT: ret i1 [[RES_2]]
375 ; CHECK-NEXT: ret i1 [[RES_2]]
[all …]
H A Dne.ll14 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
15 ; CHECK-NEXT: ret i1 [[RES_2]]
55 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
57 ; CHECK-NEXT: [[RES_3:%.*]] = xor i1 [[RES_2]], [[C_3]]
160 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
161 ; CHECK-NEXT: ret i1 [[RES_2]]
201 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
203 ; CHECK-NEXT: [[RES_3:%.*]] = xor i1 [[RES_2]], [[C_3]]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
/dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions-inseltpoison.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
H A Dsink-free-instructions.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
H A Dsink-free-instructions-inseltpoison.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions-inseltpoison.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
H A Dsink-free-instructions.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/ConstraintElimination/
H A Dne.ll14 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
15 ; CHECK-NEXT: ret i1 [[RES_2]]
55 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
57 ; CHECK-NEXT: [[RES_3:%.*]] = xor i1 [[RES_2]], [[C_3]]
160 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
161 ; CHECK-NEXT: ret i1 [[RES_2]]
201 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
203 ; CHECK-NEXT: [[RES_3:%.*]] = xor i1 [[RES_2]], [[C_3]]
/dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions-inseltpoison.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
H A Dsink-free-instructions.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions-inseltpoison.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
H A Dsink-free-instructions.ll17 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
18 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
30 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
31 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
60 ; NEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[TMP1]], [[ZB_2]]
61 ; NEON-NEXT: ret <8 x i16> [[RES_2]]
73 ; NONEON-NEXT: [[RES_2:%.*]] = sub <8 x i16> [[ZA]], [[ZB_2]]
74 ; NONEON-NEXT: ret <8 x i16> [[RES_2]]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/ConstraintElimination/
H A Dne.ll14 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
15 ; CHECK-NEXT: ret i1 [[RES_2]]
55 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
57 ; CHECK-NEXT: [[RES_3:%.*]] = xor i1 [[RES_2]], [[C_3]]
160 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
161 ; CHECK-NEXT: ret i1 [[RES_2]]
201 ; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_2]]
203 ; CHECK-NEXT: [[RES_3:%.*]] = xor i1 [[RES_2]], [[C_3]]

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