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Searched refs:RHSReg (Results 1 – 25 of 85) sorted by relevance

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/dports/devel/avr-gdb/gdb-7.3.1/sim/arm/
H A Darmemu.h310 #define RHSReg (BITS ( 0, 3)) macro
336 #define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
338 #define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
341 #define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
343 #define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
351 #define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
354 #define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
363 #define SWAPSRC (state->Reg[RHSReg])
/dports/devel/gdb761/gdb-7.6.1/sim/arm/
H A Darmemu.h309 #define RHSReg (BITS ( 0, 3)) macro
335 #define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
337 #define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
340 #define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
342 #define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
350 #define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
353 #define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
362 #define SWAPSRC (state->Reg[RHSReg])
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/arm/
H A Darmemu.h310 #define RHSReg (BITS ( 0, 3)) macro
336 #define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
338 #define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
341 #define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
343 #define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
351 #define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
354 #define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
363 #define SWAPSRC (state->Reg[RHSReg])
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/arm/
H A Darmemu.h310 #define RHSReg (BITS ( 0, 3)) macro
336 #define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
338 #define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
341 #define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
343 #define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
351 #define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
354 #define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
363 #define SWAPSRC (state->Reg[RHSReg])
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1242 if (!RHSReg) in emitAddSub()
1262 if (!RHSReg) in emitAddSub()
1301 if (!RHSReg) in emitAddSub()
1306 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1319 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1403 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1446 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1541 if (!RHSReg) in emitFCmp()
1649 if (!RHSReg) in emitLogicalOp()
1676 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1242 if (!RHSReg) in emitAddSub()
1262 if (!RHSReg) in emitAddSub()
1301 if (!RHSReg) in emitAddSub()
1306 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1319 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1403 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1446 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1541 if (!RHSReg) in emitFCmp()
1649 if (!RHSReg) in emitLogicalOp()
1676 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1217 if (!RHSReg) in emitAddSub()
1236 if (!RHSReg) in emitAddSub()
1271 if (!RHSReg) in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1286 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1369 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1411 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1504 if (!RHSReg) in emitFCmp()
1606 if (!RHSReg) in emitLogicalOp()
1629 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp1217 if (!RHSReg) in emitAddSub()
1236 if (!RHSReg) in emitAddSub()
1271 if (!RHSReg) in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1286 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1369 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1411 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1504 if (!RHSReg) in emitFCmp()
1606 if (!RHSReg) in emitLogicalOp()
1629 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1242 if (!RHSReg) in emitAddSub()
1262 if (!RHSReg) in emitAddSub()
1301 if (!RHSReg) in emitAddSub()
1306 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1319 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1403 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1446 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1541 if (!RHSReg) in emitFCmp()
1649 if (!RHSReg) in emitLogicalOp()
1676 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp1242 if (!RHSReg) in emitAddSub()
1262 if (!RHSReg) in emitAddSub()
1301 if (!RHSReg) in emitAddSub()
1306 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1319 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1403 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1446 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1541 if (!RHSReg) in emitFCmp()
1649 if (!RHSReg) in emitLogicalOp()
1676 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp1244 if (!RHSReg) in emitAddSub()
1264 if (!RHSReg) in emitAddSub()
1303 if (!RHSReg) in emitAddSub()
1308 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1321 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1405 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1448 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1543 if (!RHSReg) in emitFCmp()
1651 if (!RHSReg) in emitLogicalOp()
1678 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1217 if (!RHSReg) in emitAddSub()
1236 if (!RHSReg) in emitAddSub()
1271 if (!RHSReg) in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1286 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1369 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1411 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1504 if (!RHSReg) in emitFCmp()
1606 if (!RHSReg) in emitLogicalOp()
1629 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1244 if (!RHSReg) in emitAddSub()
1264 if (!RHSReg) in emitAddSub()
1303 if (!RHSReg) in emitAddSub()
1308 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1321 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1405 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1448 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1543 if (!RHSReg) in emitFCmp()
1651 if (!RHSReg) in emitLogicalOp()
1678 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1217 if (!RHSReg) in emitAddSub()
1236 if (!RHSReg) in emitAddSub()
1271 if (!RHSReg) in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1286 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1369 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1411 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1504 if (!RHSReg) in emitFCmp()
1606 if (!RHSReg) in emitLogicalOp()
1629 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1217 if (!RHSReg) in emitAddSub()
1236 if (!RHSReg) in emitAddSub()
1271 if (!RHSReg) in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1286 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1369 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1411 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1504 if (!RHSReg) in emitFCmp()
1606 if (!RHSReg) in emitLogicalOp()
1629 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1244 if (!RHSReg) in emitAddSub()
1264 if (!RHSReg) in emitAddSub()
1303 if (!RHSReg) in emitAddSub()
1308 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1321 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1405 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1448 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1543 if (!RHSReg) in emitFCmp()
1651 if (!RHSReg) in emitLogicalOp()
1678 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1242 if (!RHSReg) in emitAddSub()
1262 if (!RHSReg) in emitAddSub()
1301 if (!RHSReg) in emitAddSub()
1306 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1319 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1403 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1446 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1541 if (!RHSReg) in emitFCmp()
1649 if (!RHSReg) in emitLogicalOp()
1676 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp1207 if (!RHSReg) in emitAddSub()
1227 if (!RHSReg) in emitAddSub()
1266 if (!RHSReg) in emitAddSub()
1271 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1284 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1368 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1411 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1506 if (!RHSReg) in emitFCmp()
1614 if (!RHSReg) in emitLogicalOp()
1641 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp1211 if (!RHSReg) in emitAddSub()
1231 if (!RHSReg) in emitAddSub()
1270 if (!RHSReg) in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1288 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1372 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1415 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1510 if (!RHSReg) in emitFCmp()
1618 if (!RHSReg) in emitLogicalOp()
1645 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp1211 if (!RHSReg) in emitAddSub()
1231 if (!RHSReg) in emitAddSub()
1270 if (!RHSReg) in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1288 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1372 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1415 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1510 if (!RHSReg) in emitFCmp()
1618 if (!RHSReg) in emitLogicalOp()
1645 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1217 if (!RHSReg) in emitAddSub()
1236 if (!RHSReg) in emitAddSub()
1271 if (!RHSReg) in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1286 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1369 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1411 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1504 if (!RHSReg) in emitFCmp()
1606 if (!RHSReg) in emitLogicalOp()
1629 if (!RHSReg) in emitLogicalOp()
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/
H A DARMInstructionSelector.cpp54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
392 unsigned LHSReg, unsigned RHSReg, in validOpRegPair() argument
395 return MRI.getType(LHSReg) == MRI.getType(RHSReg) && in validOpRegPair()
397 validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID); in validOpRegPair()
434 auto RHSReg = MIB->getOperand(3).getReg(); in selectCmp() local
435 if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize, in selectCmp()
445 if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg, in selectCmp()
452 RHSReg, ZeroReg)) in selectCmp()
454 if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg, in selectCmp()
466 unsigned LHSReg, unsigned RHSReg, in insertComparison() argument
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/
H A DARMInstructionSelector.cpp54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
450 unsigned LHSReg, unsigned RHSReg, in validOpRegPair() argument
453 return MRI.getType(LHSReg) == MRI.getType(RHSReg) && in validOpRegPair()
455 validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID); in validOpRegPair()
492 auto RHSReg = MIB->getOperand(3).getReg(); in selectCmp() local
493 if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize, in selectCmp()
503 if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg, in selectCmp()
510 RHSReg, ZeroReg)) in selectCmp()
512 if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg, in selectCmp()
524 unsigned LHSReg, unsigned RHSReg, in insertComparison() argument
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
502 unsigned LHSReg, unsigned RHSReg, in validOpRegPair() argument
505 return MRI.getType(LHSReg) == MRI.getType(RHSReg) && in validOpRegPair()
507 validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID); in validOpRegPair()
544 auto RHSReg = MIB.getReg(3); in selectCmp() local
545 if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize, in selectCmp()
555 if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg, in selectCmp()
562 RHSReg, ZeroReg)) in selectCmp()
564 if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg, in selectCmp()
576 unsigned LHSReg, unsigned RHSReg, in insertComparison() argument
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
504 unsigned LHSReg, unsigned RHSReg, in validOpRegPair() argument
507 return MRI.getType(LHSReg) == MRI.getType(RHSReg) && in validOpRegPair()
509 validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID); in validOpRegPair()
546 auto RHSReg = MIB.getReg(3); in selectCmp() local
547 if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize, in selectCmp()
557 if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg, in selectCmp()
564 RHSReg, ZeroReg)) in selectCmp()
566 if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg, in selectCmp()
578 unsigned LHSReg, unsigned RHSReg, in insertComparison() argument
[all …]

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