Home
last modified time | relevance | path

Searched refs:RLDICR (Results 1 – 25 of 449) sorted by relevance

12345678910>>...18

/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
H A Djump-tables-collapse-rotate-remove-SrcMI.mir5 # collapse RLDICL/RLDICR into RLDIC when possible, but it missed removing the
42 %3:g8rc = RLDICR %2, 2, 61
53 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
H A Dlivephysregs.mir8 # CHECK: $x4 = RLDICR killed $x6, 16, 47
29 $x4 = RLDICR killed $x6, 16, 47
49 $x4 = RLDICR killed $x6, 16, 47
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
H A Djump-tables-collapse-rotate-remove-SrcMI.mir5 # collapse RLDICL/RLDICR into RLDIC when possible, but it missed removing the
42 %3:g8rc = RLDICR %2, 2, 61
53 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
H A Djump-tables-collapse-rotate-remove-SrcMI.mir5 # collapse RLDICL/RLDICR into RLDIC when possible, but it missed removing the
42 %3:g8rc = RLDICR %2, 2, 61
53 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
H A Djump-tables-collapse-rotate-remove-SrcMI.mir5 # collapse RLDICL/RLDICR into RLDIC when possible, but it missed removing the
42 %3:g8rc = RLDICR %2, 2, 61
53 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
H A Djump-tables-collapse-rotate-remove-SrcMI.mir5 # collapse RLDICL/RLDICR into RLDIC when possible, but it missed removing the
42 %3:g8rc = RLDICR %2, 2, 61
53 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
H A Djump-tables-collapse-rotate-remove-SrcMI.mir5 # collapse RLDICL/RLDICR into RLDIC when possible, but it missed removing the
42 %3:g8rc = RLDICR %2, 2, 61
53 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
H A Djump-tables-collapse-rotate-remove-SrcMI.mir5 # collapse RLDICL/RLDICR into RLDIC when possible, but it missed removing the
42 %3:g8rc = RLDICR %2, 2, 61
53 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
H A Djump-tables-collapse-rotate-remove-SrcMI.mir5 # collapse RLDICL/RLDICR into RLDIC when possible, but it missed removing the
42 %3:g8rc = RLDICR %2, 2, 61
53 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
H A Djump-tables-collapse-rotate-remove-SrcMI.mir5 # collapse RLDICL/RLDICR into RLDIC when possible, but it missed removing the
42 %3:g8rc = RLDICR %2, 2, 61
53 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
H A Djump-tables-collapse-rotate-remove-SrcMI.mir5 # collapse RLDICL/RLDICR into RLDIC when possible, but it missed removing the
42 %3:g8rc = RLDICR %2, 2, 61
53 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dpeephole-miscompile-extswsli.mir24 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
25 ; CHECK: $x3 = COPY [[RLDICR]]
26 ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
53 %12:g8rc = RLDICR %11, 2, 61
55 %9:g8rc = RLDICR %0, 2, 61
H A Djump-tables-collapse-rotate-remove-SrcMI.mir5 # collapse RLDICL/RLDICR into RLDIC when possible, but it missed removing the
42 %3:g8rc = RLDICR %2, 2, 61
53 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61

12345678910>>...18