/dports/lang/gomacro/gomacro-2.7-304-g2f4dc7c/jit/amd64/ |
H A D | machine.go | 39 RLo RegId = RAX const 46 RAX - RLo: "%al", 47 RCX - RLo: "%cl", 48 RDX - RLo: "%dl", 49 RBX - RLo: "%bl", 64 RAX - RLo: "%ax", 65 RCX - RLo: "%cx", 66 RDX - RLo: "%dx", 67 RBX - RLo: "%bx", 68 RSP - RLo: "%sp", [all …]
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H A D | arch.go | 43 RLo: RLo, 54 return id >= RLo && id <= RHi 59 if id >= RLo && id <= RHi { 60 s = regName8[id-RLo] 77 id -= RLo
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H A D | zexec_test.go | 92 for id := RLo; id <= RHi; id++ { 162 for id := RLo; id <= RHi; id++ {
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/dports/lang/gomacro/gomacro-2.7-304-g2f4dc7c/jit/arm64/_template/ |
H A D | gen_op3.go | 111 rlok := arch.MakeReg(arch.RLo, k) 136 rlo := arch.MakeReg(arch.RLo, k) 163 rlo := arch.MakeReg(arch.RLo, k) 165 for r := arch.RLo; r < arch.RHi; r++ { 168 for r := arch.RLo; r < arch.RHi; r++ { 187 rlo := arch.MakeReg(arch.RLo, k) 189 for r := arch.RLo; r < arch.RHi; r++ { 192 for r := arch.RLo; r < arch.RHi; r++ { 211 rlo := arch.MakeReg(arch.RLo, k) 213 for r := arch.RLo; r < arch.RHi; r++ { [all …]
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H A D | gen_op2.go | 96 rlo1 := arch.MakeReg(arch.RLo, k1) 97 rlo2 := arch.MakeReg(arch.RLo, k2) 98 for id := arch.RLo; id < arch.RHi; id++ { 102 for id := arch.RLo; id < arch.RHi; id++ { 111 rlo := arch.MakeReg(arch.RLo, k) 112 for id := arch.RLo; id < arch.RHi; id++ { 116 for id := arch.RLo; id < arch.RHi; id++ { 130 rlo := arch.MakeReg(arch.RLo, k) 137 for id := arch.RLo; id < arch.RHi; id++ {
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/dports/lang/gomacro/gomacro-2.7-304-g2f4dc7c/jit/amd64/_template/ |
H A D | gen_op3.go | 96 rbase := amd64.MakeReg(amd64.RLo, amd64.Uintptr) 98 rdst := amd64.MakeReg(amd64.RLo, k) 103 for r1 := amd64.RLo; r1 <= amd64.RHi; r1++ { 110 for r2 := amd64.RLo; r2 <= amd64.RHi; r2++ { 121 for r3 := amd64.RLo; r3 <= amd64.RHi; r3++ { 141 rsrc := amd64.MakeReg(amd64.RLo, k) 148 for r1 := amd64.RLo; r1 <= amd64.RHi; r1++ { 155 for r2 := amd64.RLo; r2 <= amd64.RHi; r2++ { 162 for r3 := amd64.RLo; r3 <= amd64.RHi; r3++ { 194 for r1 := amd64.RLo; r1 <= amd64.RHi; r1++ { [all …]
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H A D | gen_op2.go | 112 for r := amd64.RLo; r <= amd64.RHi; r++ { 125 for src := amd64.RLo; src <= amd64.RHi; src++ { 126 for dst := amd64.RLo; dst <= amd64.RHi; dst++ { 145 for src := amd64.RLo; src <= amd64.RHi; src++ { 146 for dst := amd64.RLo; dst <= amd64.RHi; dst++ { 171 for src := amd64.RLo; src <= amd64.RHi; src++ { 172 for dst := amd64.RLo; dst <= amd64.RHi; dst++ { 203 for src := amd64.RLo; src <= amd64.RHi; src++ { 204 for dst := amd64.RLo; dst <= amd64.RHi; dst++ { 233 for dst := amd64.RLo; dst <= amd64.RHi; dst++ { [all …]
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H A D | gen_op1.go | 87 for r := amd64.RLo; r <= amd64.RHi; r++ { 108 for r := amd64.RLo; r <= amd64.RHi; r++ {
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/dports/lang/gomacro/gomacro-2.7-304-g2f4dc7c/jit/arm64/ |
H A D | arch.go | 43 RLo: RLo, 47 RAllocFirst: RLo, 52 return id >= RLo && id < RHi // XZR/XSP is valid only in few, hand-checked cases 57 if id >= RLo && id <= RHi { 74 if id >= RLo && id <= RHi {
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H A D | machine.go | 57 RLo = X0 const 72 for id := RLo; id < RHi; id++ {
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H A D | z_test.go | 38 id := RLo 105 id := RLo 144 id := RLo
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/dports/lang/gomacro/gomacro-2.7-304-g2f4dc7c/jit/_disasm/ |
H A D | zarm64_test.go | 28 for id := RLo; id+2 <= RHi; id++ { 84 if id == RLo || id == RHi { 91 r := MakeReg(RLo, Uint64) 114 src := MakeReg(RLo, skind) 116 dst := MakeReg(RLo, dkind) 127 id := RLo
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H A D | z_test.go | 33 for id := cfg.RLo; id+2 <= cfg.RHi; id++ { 89 if id == cfg.RLo || id == cfg.RHi {
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H A D | zamd64_test.go | 46 for id := RLo; id <= RHi; id++ { 64 for id := RLo; id <= RHi; id++ {
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/dports/lang/gomacro/gomacro-2.7-304-g2f4dc7c/jit/ |
H A D | z_test.go | 49 r := MakeReg(c.RLo, Uint64) 76 r1 := MakeReg(c.RLo, Uint64) 77 r2 := MakeReg(c.RLo+1, Uint64)
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/dports/devel/intel-graphics-compiler/intel-graphics-compiler-igc-1.0.9636/IGC/BiFModule/Implementation/IMF/FP64/ |
H A D | cosh_d_la.cl | 311 double R, RHi, RLo, scale; 343 RLo = (M * ((__constant double *) __dcosh_la_CoutTab)[139]); 345 R = (R - RLo); 388 RLo = M * ((__constant double *) __dcosh_la_CoutTab)[139]; 390 R = (R - RLo);
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H A D | exp10_d_la.cl | 384 double R, RHi, RLo, p, scale, tmp3, dbIn; 406 RLo = (w * ((__constant double *) _imldExp10HATab_v2)[139]); 408 R = (R - RLo);
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H A D | sinh_d_la.cl | 403 double R, RHi, RMid, RLo; 458 RLo = v3;; 530 pLo = (RLo * TsL); 534 pLo += (RLo * TsH);
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/dports/lang/gomacro/gomacro-2.7-304-g2f4dc7c/jit/common/ |
H A D | reg.go | 55 RLo, RHi, RSP, RVAR RegId member
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H A D | asm.go | 84 asm.regIds.rlo = config.RLo
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/dports/lang/gcc48/gcc-4.8.5/gcc/ada/ |
H A D | sem_eval.adb | 996 RLo, RHi : Uint; variable 1003 Determine_Range (R, ROK, RLo, RHi, Assume_Valid); 1006 Single := (LLo = LHi) and then (RLo = RHi); 1008 if LHi < RLo then 1010 Diff.all := RLo - LLo; 1017 Diff.all := LLo - RLo; 1022 elsif Single and then LLo = RLo then 1034 elsif LHi = RLo then
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/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/ada/ |
H A D | sem_eval.adb | 996 RLo, RHi : Uint; variable 1003 Determine_Range (R, ROK, RLo, RHi, Assume_Valid); 1006 Single := (LLo = LHi) and then (RLo = RHi); 1008 if LHi < RLo then 1010 Diff.all := RLo - LLo; 1017 Diff.all := LLo - RLo; 1022 elsif Single and then LLo = RLo then 1034 elsif LHi = RLo then
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/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/ada/ |
H A D | sem_eval.adb | 997 RLo, RHi : Uint; variable 1004 Determine_Range (R, ROK, RLo, RHi, Assume_Valid); 1007 Single := (LLo = LHi) and then (RLo = RHi); 1009 if LHi < RLo then 1011 Diff.all := RLo - LLo; 1018 Diff.all := LLo - RLo; 1023 elsif Single and then LLo = RLo then 1035 elsif LHi = RLo then
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/dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/ARM/ |
H A D | ARMInstrInfo.td | 4317 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4319 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4328 def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4329 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4330 def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4331 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4332 def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4333 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4335 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4394 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, [all …]
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/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/ARM/ |
H A D | ARMInstrInfo.td | 4317 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4319 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4328 def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4329 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4330 def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4331 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4332 def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4333 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4335 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4394 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, [all …]
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