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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp90 return RSI.Instr == Instr; in operator ==()
241 RSI->Instr->eraseFromParent(); in RebuildVector()
244 RSI->Instr = NewMI; in RebuildVector()
246 RSI->UndefReg = UpdatedUndef; in RebuildVector()
302 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
326 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
329 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
330 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
382 trackRSI(RSI); in runOnMachineFunction()
390 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp90 return RSI.Instr == Instr; in operator ==()
241 RSI->Instr->eraseFromParent(); in RebuildVector()
244 RSI->Instr = NewMI; in RebuildVector()
246 RSI->UndefReg = UpdatedUndef; in RebuildVector()
302 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
326 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
329 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
330 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
382 trackRSI(RSI); in runOnMachineFunction()
390 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp90 return RSI.Instr == Instr; in operator ==()
241 RSI->Instr->eraseFromParent(); in RebuildVector()
244 RSI->Instr = NewMI; in RebuildVector()
246 RSI->UndefReg = UpdatedUndef; in RebuildVector()
302 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
326 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
329 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
330 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
382 trackRSI(RSI); in runOnMachineFunction()
390 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp90 return RSI.Instr == Instr; in operator ==()
241 RSI->Instr->eraseFromParent(); in RebuildVector()
244 RSI->Instr = NewMI; in RebuildVector()
246 RSI->UndefReg = UpdatedUndef; in RebuildVector()
302 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
326 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
329 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
330 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
382 trackRSI(RSI); in runOnMachineFunction()
390 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp96 return RSI.Instr == Instr; in operator ==()
247 RSI->Instr->eraseFromParent(); in RebuildVector()
250 RSI->Instr = NewMI; in RebuildVector()
252 RSI->UndefReg = UpdatedUndef; in RebuildVector()
308 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
332 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
335 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
336 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
388 trackRSI(RSI); in runOnMachineFunction()
396 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp96 return RSI.Instr == Instr; in operator ==()
247 RSI->Instr->eraseFromParent(); in RebuildVector()
250 RSI->Instr = NewMI; in RebuildVector()
252 RSI->UndefReg = UpdatedUndef; in RebuildVector()
308 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
332 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
335 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
336 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
388 trackRSI(RSI); in runOnMachineFunction()
396 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp89 return RSI.Instr == Instr; in operator ==()
245 RSI->Instr->eraseFromParent(); in RebuildVector()
248 RSI->Instr = NewMI; in RebuildVector()
250 RSI->UndefReg = UpdatedUndef; in RebuildVector()
306 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
330 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
333 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
334 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
386 trackRSI(RSI); in runOnMachineFunction()
394 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp89 return RSI.Instr == Instr; in operator ==()
245 RSI->Instr->eraseFromParent(); in RebuildVector()
248 RSI->Instr = NewMI; in RebuildVector()
250 RSI->UndefReg = UpdatedUndef; in RebuildVector()
306 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
330 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
333 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
334 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
386 trackRSI(RSI); in runOnMachineFunction()
394 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp70 return RSI.Instr == Instr; in operator ==()
226 RSI->Instr->eraseFromParent(); in RebuildVector()
229 RSI->Instr = NewMI; in RebuildVector()
231 RSI->UndefReg = UpdatedUndef; in RebuildVector()
287 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
311 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
314 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
315 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
367 trackRSI(RSI); in runOnMachineFunction()
375 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp70 return RSI.Instr == Instr; in operator ==()
226 RSI->Instr->eraseFromParent(); in RebuildVector()
229 RSI->Instr = NewMI; in RebuildVector()
231 RSI->UndefReg = UpdatedUndef; in RebuildVector()
287 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
311 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
314 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
315 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
367 trackRSI(RSI); in runOnMachineFunction()
375 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp70 return RSI.Instr == Instr; in operator ==()
226 RSI->Instr->eraseFromParent(); in RebuildVector()
229 RSI->Instr = NewMI; in RebuildVector()
231 RSI->UndefReg = UpdatedUndef; in RebuildVector()
287 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
311 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
314 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
315 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
367 trackRSI(RSI); in runOnMachineFunction()
375 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp89 return RSI.Instr == Instr; in operator ==()
245 RSI->Instr->eraseFromParent(); in RebuildVector()
248 RSI->Instr = NewMI; in RebuildVector()
250 RSI->UndefReg = UpdatedUndef; in RebuildVector()
306 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
330 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
333 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
334 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
386 trackRSI(RSI); in runOnMachineFunction()
394 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp70 return RSI.Instr == Instr; in operator ==()
226 RSI->Instr->eraseFromParent(); in RebuildVector()
229 RSI->Instr = NewMI; in RebuildVector()
231 RSI->UndefReg = UpdatedUndef; in RebuildVector()
287 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
311 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
314 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
315 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
367 trackRSI(RSI); in runOnMachineFunction()
375 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp70 return RSI.Instr == Instr; in operator ==()
226 RSI->Instr->eraseFromParent(); in RebuildVector()
229 RSI->Instr = NewMI; in RebuildVector()
231 RSI->UndefReg = UpdatedUndef; in RebuildVector()
287 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
311 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
314 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
315 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
367 trackRSI(RSI); in runOnMachineFunction()
375 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp70 return RSI.Instr == Instr; in operator ==()
226 RSI->Instr->eraseFromParent(); in RebuildVector()
229 RSI->Instr = NewMI; in RebuildVector()
231 RSI->UndefReg = UpdatedUndef; in RebuildVector()
287 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
311 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
314 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
315 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
367 trackRSI(RSI); in runOnMachineFunction()
375 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp70 return RSI.Instr == Instr; in operator ==()
226 RSI->Instr->eraseFromParent(); in RebuildVector()
229 RSI->Instr = NewMI; in RebuildVector()
231 RSI->UndefReg = UpdatedUndef; in RebuildVector()
287 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
311 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
314 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
315 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
367 trackRSI(RSI); in runOnMachineFunction()
375 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp70 return RSI.Instr == Instr; in operator ==()
226 RSI->Instr->eraseFromParent(); in RebuildVector()
229 RSI->Instr = NewMI; in RebuildVector()
231 RSI->UndefReg = UpdatedUndef; in RebuildVector()
287 if (RSI == CompatibleRSI) in tryMergeUsingCommonSlot()
311 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { in trackRSI()
314 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
315 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
367 trackRSI(RSI); in runOnMachineFunction()
375 trackRSI(RSI); in runOnMachineFunction()
[all …]
/dports/archivers/ppmd-7z/p7zip_9.04/Asm/x64/
H A D7zCrcT8U.asm9 movzx EDX, BYTE [RSI]
10 inc RSI
25 ; push RSI
30 ; RSI = BUF
38 test RSI, 7
51 add R9, RSI
52 xor EAX, [RSI]
77 add RSI, 8
82 cmp RSI, R9
84 xor EAX, [RSI]
[all …]
/dports/accessibility/kmousetool/kmousetool-21.12.3/kmousetool/
H A Dorg.kde.kmousetool.desktop6 Comment=Clicks the mouse for you, reducing the effects of RSI
7 Comment[ar]=ينقر على الفأرة بدلاً عنك، مُخَفِّفاً عنك تأثيرات RSI
12 Comment[cs]=Kliká za vás myší, omezuje tak efekt RSI
30 Comment[hr]=Pritišće miš za vas i time smanjuje efekte RSI-a
35 Comment[ja]=RSI (反復運動過多損傷) を防ぐために、あなたの代わりにマウスをクリック
39 Comment[ku]=Ji bo we mişkê ditikîne, efekta RSI kêmtir dike
56 Comment[sk]=Kliká za vás myšou, uľahčuje bolesti RSI
64 Comment[ta]=Clicks the mouse for you, reducing the effects of RSI RSI
69 Comment[vi]=Bấm chuột giúp bạn, giảm tác động của RSI
71 Comment[zh_CN]=为您点击鼠标，减轻肢体重复性劳损 (RSI) 效应
[all …]
/dports/finance/R-cran-TTR/TTR/man/
H A DRSI.Rd2 % Please edit documentation in R/RSI.R
3 \name{RSI}
4 \alias{RSI}
7 RSI(price, n = 14, maType, ...)
27 \code{try.xts} fails) containing the RSI values.
35 The RSI calculation is \code{RSI = 100 - 100 / ( 1 + RS )}, where \code{RS}
47 on RSI values.
55 rsi <- RSI(price)
69 \url{https://www.fmlabs.com/reference/RSI.htm}\cr
73 \cr Stochastic RSI:\cr
[all …]
/dports/math/tblis/tblis-1.2.0/src/configs/knl/
H A Dbli_dpackm_opt_24x8.c129 MOV(RSI, VAR(n)) in bli_dpackm_8xk_opt()
136 TEST(RSI, RSI) in bli_dpackm_8xk_opt()
153 MOV(RDX, RSI) in bli_dpackm_8xk_opt()
155 SAR(RSI, IMM(3)) in bli_dpackm_8xk_opt()
200 MOV(RDX, RSI) in bli_dpackm_8xk_opt()
202 SAR(RSI, IMM(3)) in bli_dpackm_8xk_opt()
225 SHLX(RSI, RSI, RDX) in bli_dpackm_8xk_opt()
321 MOV(RSI, VAR(n)) in bli_dpackm_24xk_opt()
337 TEST(RSI, RSI) in bli_dpackm_24xk_opt()
372 TEST(RSI, RSI) in bli_dpackm_24xk_opt()
[all …]
/dports/security/vault/vault-1.8.2/vendor/github.com/influxdata/influxdb/query/internal/gota/
H A Drsi.go4 type RSI struct { struct
11 func NewRSI(inTimePeriod int, warmType WarmupType) *RSI {
14 return &RSI{
21 func (rsi RSI) WarmCount() int { argument
26 func (rsi RSI) Warmed() bool { argument
31 func (rsi RSI) Last() float64 { argument
36 func (rsi *RSI) Add(v float64) float64 { argument
/dports/net-mgmt/prometheus2/prometheus-2.30.3/vendor/github.com/influxdata/influxdb/query/internal/gota/
H A Drsi.go4 type RSI struct { struct
11 func NewRSI(inTimePeriod int, warmType WarmupType) *RSI {
14 return &RSI{
21 func (rsi RSI) WarmCount() int { argument
26 func (rsi RSI) Warmed() bool { argument
31 func (rsi RSI) Last() float64 { argument
36 func (rsi *RSI) Add(v float64) float64 { argument
/dports/net-p2p/go-ethereum/go-ethereum-1.10.14/vendor/github.com/influxdata/influxdb/query/internal/gota/
H A Drsi.go4 type RSI struct { struct
11 func NewRSI(inTimePeriod int, warmType WarmupType) *RSI {
14 return &RSI{
21 func (rsi RSI) WarmCount() int { argument
26 func (rsi RSI) Warmed() bool { argument
31 func (rsi RSI) Last() float64 { argument
36 func (rsi *RSI) Add(v float64) float64 { argument
/dports/net-mgmt/bosun/bosun-0.9.0-preview/vendor/github.com/influxdata/influxdb/query/internal/gota/
H A Drsi.go4 type RSI struct { struct
11 func NewRSI(inTimePeriod int, warmType WarmupType) *RSI {
14 return &RSI{
21 func (rsi RSI) WarmCount() int { argument
26 func (rsi RSI) Warmed() bool { argument
31 func (rsi RSI) Last() float64 { argument
36 func (rsi *RSI) Add(v float64) float64 { argument

12345678910>>...97