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Searched refs:R_12 (Results 1 – 25 of 38) sorted by relevance

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/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Ds390-opc.c50 #define R_12 2 /* GPR starting at position 12 */ macro
231 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
232 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
233 #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */
234 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
243 #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
290 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
294 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
296 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
298 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
[all …]
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Ds390-opc.c47 #define R_12 2 /* GPR starting at position 12 */ macro
177 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
203 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
206 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
208 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
209 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
212 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
213 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
219 #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
237 #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
[all …]
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Ds390-opc.c47 #define R_12 2 /* GPR starting at position 12 */ macro
177 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
203 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
206 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
208 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
209 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
212 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
213 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
219 #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
237 #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Ds390-opc.c47 #define R_12 2 /* GPR starting at position 12 */ macro
177 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
203 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
206 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
208 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
209 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
212 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
213 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
219 #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
237 #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
[all …]
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Ds390-opc.c47 #define R_12 2 /* GPR starting at position 12 */ macro
184 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
213 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
216 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
218 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
219 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
223 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
224 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
231 #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
249 #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
[all …]
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/
H A Ds390-opc.c49 #define R_12 2 /* GPR starting at position 12 */ macro
304 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
305 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
307 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
317 #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
318 #define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */
387 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
393 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
394 #define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */
396 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
[all …]
/dports/devel/gdb/gdb-11.1/opcodes/
H A Ds390-opc.c49 #define R_12 2 /* GPR starting at position 12 */ macro
304 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
305 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
307 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
317 #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
318 #define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */
387 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
393 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
394 #define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */
396 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
[all …]
/dports/devel/gnulibiberty/binutils-2.37/opcodes/
H A Ds390-opc.c49 #define R_12 2 /* GPR starting at position 12 */ macro
304 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
305 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
307 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
317 #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
318 #define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */
387 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
393 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
394 #define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */
396 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
[all …]
/dports/devel/binutils/binutils-2.37/opcodes/
H A Ds390-opc.c49 #define R_12 2 /* GPR starting at position 12 */ macro
304 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
305 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
307 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
317 #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
318 #define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */
387 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
393 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
394 #define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */
396 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
[all …]
/dports/devel/gdb761/gdb-7.6.1/opcodes/
H A Ds390-opc.c50 #define R_12 2 /* GPR starting at position 12 */ macro
288 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
289 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
290 #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */
291 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
300 #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
371 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
378 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
379 #define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */
381 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
[all …]
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/
H A Ds390-opc.c49 #define R_12 2 /* GPR starting at position 12 */ macro
300 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
301 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
303 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
313 #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
379 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
385 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
386 #define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */
388 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
391 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
[all …]
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/
H A Ds390-opc.c49 #define R_12 2 /* GPR starting at position 12 */ macro
300 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
301 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
303 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
313 #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
379 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
385 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
386 #define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */
388 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
391 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/s390/kernel/
H A Ddis.c106 R_12, /* GPR starting at position 12 */ enumerator
168 [R_12] = { 4, 12, OPERAND_GPR },
203 [INSTR_RIE_RRI0] = { R_8, R_12, I16_16, 0, 0, 0 },
204 [INSTR_RIE_RRP] = { R_8, R_12, J16_16, 0, 0, 0 },
249 [INSTR_RRS_RRRDU] = { R_8, R_12, U4_32, D_20, B_16 },
252 [INSTR_RR_RR] = { R_8, R_12, 0, 0, 0, 0 },
254 [INSTR_RR_UR] = { U4_8, R_12, 0, 0, 0, 0 },
255 [INSTR_RSI_RRP] = { R_8, R_12, J16_16, 0, 0, 0 },
267 [INSTR_RS_RRRD] = { R_8, R_12, D_20, B_16, 0, 0 },
311 [INSTR_VRR_VRR] = { V_8, R_12, R_16, 0, 0, 0 },
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/s390/kernel/
H A Ddis.c106 R_12, /* GPR starting at position 12 */ enumerator
168 [R_12] = { 4, 12, OPERAND_GPR },
203 [INSTR_RIE_RRI0] = { R_8, R_12, I16_16, 0, 0, 0 },
204 [INSTR_RIE_RRP] = { R_8, R_12, J16_16, 0, 0, 0 },
249 [INSTR_RRS_RRRDU] = { R_8, R_12, U4_32, D_20, B_16 },
252 [INSTR_RR_RR] = { R_8, R_12, 0, 0, 0, 0 },
254 [INSTR_RR_UR] = { U4_8, R_12, 0, 0, 0, 0 },
255 [INSTR_RSI_RRP] = { R_8, R_12, J16_16, 0, 0, 0 },
267 [INSTR_RS_RRRD] = { R_8, R_12, D_20, B_16, 0, 0 },
311 [INSTR_VRR_VRR] = { V_8, R_12, R_16, 0, 0, 0 },
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/arch/s390/kernel/
H A Ddis.c106 R_12, /* GPR starting at position 12 */ enumerator
168 [R_12] = { 4, 12, OPERAND_GPR },
203 [INSTR_RIE_RRI0] = { R_8, R_12, I16_16, 0, 0, 0 },
204 [INSTR_RIE_RRP] = { R_8, R_12, J16_16, 0, 0, 0 },
249 [INSTR_RRS_RRRDU] = { R_8, R_12, U4_32, D_20, B_16 },
252 [INSTR_RR_RR] = { R_8, R_12, 0, 0, 0, 0 },
254 [INSTR_RR_UR] = { U4_8, R_12, 0, 0, 0, 0 },
255 [INSTR_RSI_RRP] = { R_8, R_12, J16_16, 0, 0, 0 },
267 [INSTR_RS_RRRD] = { R_8, R_12, D_20, B_16, 0, 0 },
311 [INSTR_VRR_VRR] = { V_8, R_12, R_16, 0, 0, 0 },
[all …]
/dports/emulators/qemu/qemu-6.2.0/disas/
H A Ds390.c484 #define R_12 2 /* GPR starting at position 12 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
681 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
684 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
686 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
692 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
[all …]
/dports/emulators/qemu42/qemu-4.2.1/disas/
H A Ds390.c484 #define R_12 2 /* GPR starting at position 12 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
681 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
684 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
686 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
692 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
[all …]
/dports/emulators/qemu5/qemu-5.2.0/disas/
H A Ds390.c484 #define R_12 2 /* GPR starting at position 12 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
681 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
684 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
686 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
692 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
[all …]
/dports/emulators/qemu60/qemu-6.0.0/disas/
H A Ds390.c484 #define R_12 2 /* GPR starting at position 12 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
681 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
684 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
686 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
692 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/
H A Ds390.c485 #define R_12 2 /* GPR starting at position 12 */ macro
643 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
682 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
685 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
687 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
689 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
693 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
694 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
809 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
815 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/disas/
H A Ds390.c484 #define R_12 2 /* GPR starting at position 12 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
681 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
684 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
686 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
692 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/
H A Ds390.c484 #define R_12 2 /* GPR starting at position 12 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
681 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
684 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
686 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
692 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/
H A Ds390.c484 #define R_12 2 /* GPR starting at position 12 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
681 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
684 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
686 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
692 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/
H A Ds390.c484 #define R_12 2 /* GPR starting at position 12 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
681 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
684 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
686 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
692 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
[all …]
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/
H A Ds390-dis.c437 #define R_12 2 /* GPR starting at position 12 */ macro
577 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
614 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
617 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
619 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
621 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
625 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
626 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
633 #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
652 #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
[all …]

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