Searched refs:R_CISR (Results 1 – 9 of 9) sorted by relevance
107 #define R_CISR (0x14/4) macro136 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()137 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()138 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()146 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()265 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()329 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()402 case R_CISR: /* cisr (wtc) */ in uart_write()403 s->r[R_CISR] &= ~value; in uart_write()471 s->r[R_CISR] = 0; in cadence_uart_reset()
104 #define R_CISR (0x14/4) macro133 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()134 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()135 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()143 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()262 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()326 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()399 case R_CISR: /* cisr (wtc) */ in uart_write()400 s->r[R_CISR] &= ~value; in uart_write()468 s->r[R_CISR] = 0; in cadence_uart_reset()
107 #define R_CISR (0x14/4)136 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;137 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;138 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));146 s->r[R_CISR] |= UART_INTR_TIMEOUT;265 s->r[R_CISR] |= UART_INTR_ROVR;329 s->r[R_CISR] |= UART_INTR_ROVR;402 case R_CISR: /* cisr (wtc) */403 s->r[R_CISR] &= ~value;471 s->r[R_CISR] = 0;
110 #define R_CISR (0x14/4) macro139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()140 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()149 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()288 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()352 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()439 case R_CISR: /* cisr (wtc) */ in uart_write()440 s->r[R_CISR] &= ~value; in uart_write()519 s->r[R_CISR] = 0; in cadence_uart_reset_init()
110 #define R_CISR (0x14/4) macro139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()140 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()149 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()278 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()342 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()425 case R_CISR: /* cisr (wtc) */ in uart_write()426 s->r[R_CISR] &= ~value; in uart_write()494 s->r[R_CISR] = 0; in cadence_uart_reset_init()
109 #define R_CISR (0x14/4) macro138 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()140 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()148 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()277 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()341 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()424 case R_CISR: /* cisr (wtc) */ in uart_write()425 s->r[R_CISR] &= ~value; in uart_write()493 s->r[R_CISR] = 0; in cadence_uart_reset_init()