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Searched refs:R_CISR (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/hw/char/
H A Dcadence_uart.c107 #define R_CISR (0x14/4) macro
136 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
137 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()
138 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
146 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()
265 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()
329 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()
402 case R_CISR: /* cisr (wtc) */ in uart_write()
403 s->r[R_CISR] &= ~value; in uart_write()
471 s->r[R_CISR] = 0; in cadence_uart_reset()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/char/
H A Dcadence_uart.c104 #define R_CISR (0x14/4) macro
133 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
134 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()
135 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
143 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()
262 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()
326 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()
399 case R_CISR: /* cisr (wtc) */ in uart_write()
400 s->r[R_CISR] &= ~value; in uart_write()
468 s->r[R_CISR] = 0; in cadence_uart_reset()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/char/
H A Dcadence_uart.c107 #define R_CISR (0x14/4) macro
136 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
137 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()
138 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
146 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()
265 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()
329 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()
402 case R_CISR: /* cisr (wtc) */ in uart_write()
403 s->r[R_CISR] &= ~value; in uart_write()
471 s->r[R_CISR] = 0; in cadence_uart_reset()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/char/
H A Dcadence_uart.c107 #define R_CISR (0x14/4)
136 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
137 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
138 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
146 s->r[R_CISR] |= UART_INTR_TIMEOUT;
265 s->r[R_CISR] |= UART_INTR_ROVR;
329 s->r[R_CISR] |= UART_INTR_ROVR;
402 case R_CISR: /* cisr (wtc) */
403 s->r[R_CISR] &= ~value;
471 s->r[R_CISR] = 0;
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/char/
H A Dcadence_uart.c107 #define R_CISR (0x14/4) macro
136 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
137 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()
138 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
146 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()
265 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()
329 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()
402 case R_CISR: /* cisr (wtc) */ in uart_write()
403 s->r[R_CISR] &= ~value; in uart_write()
471 s->r[R_CISR] = 0; in cadence_uart_reset()
/dports/emulators/qemu/qemu-6.2.0/hw/char/
H A Dcadence_uart.c110 #define R_CISR (0x14/4) macro
139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
140 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()
141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
149 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()
288 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()
352 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()
439 case R_CISR: /* cisr (wtc) */ in uart_write()
440 s->r[R_CISR] &= ~value; in uart_write()
519 s->r[R_CISR] = 0; in cadence_uart_reset_init()
/dports/emulators/qemu60/qemu-6.0.0/hw/char/
H A Dcadence_uart.c110 #define R_CISR (0x14/4) macro
139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
140 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()
141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
149 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()
278 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()
342 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()
425 case R_CISR: /* cisr (wtc) */ in uart_write()
426 s->r[R_CISR] &= ~value; in uart_write()
494 s->r[R_CISR] = 0; in cadence_uart_reset_init()
/dports/emulators/qemu5/qemu-5.2.0/hw/char/
H A Dcadence_uart.c109 #define R_CISR (0x14/4) macro
138 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()
140 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
148 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()
277 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()
341 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()
424 case R_CISR: /* cisr (wtc) */ in uart_write()
425 s->r[R_CISR] &= ~value; in uart_write()
493 s->r[R_CISR] = 0; in cadence_uart_reset_init()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/char/
H A Dcadence_uart.c110 #define R_CISR (0x14/4) macro
139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
140 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()
141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
149 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()
288 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()
352 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()
439 case R_CISR: /* cisr (wtc) */ in uart_write()
440 s->r[R_CISR] &= ~value; in uart_write()
519 s->r[R_CISR] = 0; in cadence_uart_reset_init()