/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/hexagon/imported/ |
H A D | subinsns.idef | 31 Q6INSN(SA1_tfr, "Rd16=Rs16", ATTRIBS(A_SUBINSN),"Tfr", { RdV=RsV;}) 32 Q6INSN(SA1_seti, "Rd16=#u6", ATTRIBS(A_SUBINSN),"Set immed", { fIMMEXT(uiV); RdV=… 33 Q6INSN(SA1_setin1, "Rd16=#-1", ATTRIBS(A_SUBINSN),"Set to -1", { RdV=-1;}) 39 Q6INSN(SA1_addsp, "Rd16=add(r29,#u6:2)", ATTRIBS(A_SUBINSN),"Add", { RdV=fREAD_SP()+uiV… 40 Q6INSN(SA1_inc, "Rd16=add(Rs16,#1)", ATTRIBS(A_SUBINSN),"Inc", { RdV=RsV+1;}) 41 Q6INSN(SA1_dec, "Rd16=add(Rs16,#-1)", ATTRIBS(A_SUBINSN),"Dec", { RdV=RsV-1;}) 43 Q6INSN(SA1_zxtb, "Rd16=and(Rs16,#255)", ATTRIBS(A_SUBINSN),"Zxtb", { RdV= fZXTN(8,32,Rs… 44 Q6INSN(SA1_and1, "Rd16=and(Rs16,#1)", ATTRIBS(A_SUBINSN),"And #1", { RdV= RsV&1;}) 45 Q6INSN(SA1_sxtb, "Rd16=sxtb(Rs16)", ATTRIBS(A_SUBINSN),"Sxtb", { RdV= fSXTN(8,32,Rs… 46 Q6INSN(SA1_zxth, "Rd16=zxth(Rs16)", ATTRIBS(A_SUBINSN),"Zxth", { RdV= fZXTN(16,32,R… [all …]
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H A D | branch.idef | 128 Q6INSN(J4_jumpseti,"Rd16=#U6 ; jump #r9:2",ATTRIBS(A_JDIR), "direct unconditional jump and set regi… 131 Q6INSN(J4_jumpsetr,"Rd16=Rs16 ; jump #r9:2",ATTRIBS(A_JDIR), "direct unconditional jump and transfe…
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/dports/emulators/qemu/qemu-6.2.0/target/hexagon/imported/ |
H A D | subinsns.idef | 31 Q6INSN(SA1_tfr, "Rd16=Rs16", ATTRIBS(A_SUBINSN),"Tfr", { RdV=RsV;}) 32 Q6INSN(SA1_seti, "Rd16=#u6", ATTRIBS(A_SUBINSN),"Set immed", { fIMMEXT(uiV); RdV=… 33 Q6INSN(SA1_setin1, "Rd16=#-1", ATTRIBS(A_SUBINSN),"Set to -1", { RdV=-1;}) 39 Q6INSN(SA1_addsp, "Rd16=add(r29,#u6:2)", ATTRIBS(A_SUBINSN),"Add", { RdV=fREAD_SP()+uiV… 40 Q6INSN(SA1_inc, "Rd16=add(Rs16,#1)", ATTRIBS(A_SUBINSN),"Inc", { RdV=RsV+1;}) 41 Q6INSN(SA1_dec, "Rd16=add(Rs16,#-1)", ATTRIBS(A_SUBINSN),"Dec", { RdV=RsV-1;}) 43 Q6INSN(SA1_zxtb, "Rd16=and(Rs16,#255)", ATTRIBS(A_SUBINSN),"Zxtb", { RdV= fZXTN(8,32,Rs… 44 Q6INSN(SA1_and1, "Rd16=and(Rs16,#1)", ATTRIBS(A_SUBINSN),"And #1", { RdV= RsV&1;}) 45 Q6INSN(SA1_sxtb, "Rd16=sxtb(Rs16)", ATTRIBS(A_SUBINSN),"Sxtb", { RdV= fSXTN(8,32,Rs… 46 Q6INSN(SA1_zxth, "Rd16=zxth(Rs16)", ATTRIBS(A_SUBINSN),"Zxth", { RdV= fZXTN(16,32,R… [all …]
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H A D | branch.idef | 128 Q6INSN(J4_jumpseti,"Rd16=#U6 ; jump #r9:2",ATTRIBS(A_JDIR), "direct unconditional jump and set regi… 131 Q6INSN(J4_jumpsetr,"Rd16=Rs16 ; jump #r9:2",ATTRIBS(A_JDIR), "direct unconditional jump and transfe…
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/dports/emulators/qemu60/qemu-6.0.0/target/hexagon/imported/ |
H A D | subinsns.idef | 31 Q6INSN(SA1_tfr, "Rd16=Rs16", ATTRIBS(A_SUBINSN),"Tfr", { RdV=RsV;}) 32 Q6INSN(SA1_seti, "Rd16=#u6", ATTRIBS(A_SUBINSN),"Set immed", { fIMMEXT(uiV); RdV=… 33 Q6INSN(SA1_setin1, "Rd16=#-1", ATTRIBS(A_SUBINSN),"Set to -1", { RdV=-1;}) 39 Q6INSN(SA1_addsp, "Rd16=add(r29,#u6:2)", ATTRIBS(A_SUBINSN),"Add", { RdV=fREAD_SP()+uiV… 40 Q6INSN(SA1_inc, "Rd16=add(Rs16,#1)", ATTRIBS(A_SUBINSN),"Inc", { RdV=RsV+1;}) 41 Q6INSN(SA1_dec, "Rd16=add(Rs16,#-1)", ATTRIBS(A_SUBINSN),"Dec", { RdV=RsV-1;}) 43 Q6INSN(SA1_zxtb, "Rd16=and(Rs16,#255)", ATTRIBS(A_SUBINSN),"Zxtb", { RdV= fZXTN(8,32,Rs… 44 Q6INSN(SA1_and1, "Rd16=and(Rs16,#1)", ATTRIBS(A_SUBINSN),"And #1", { RdV= RsV&1;}) 45 Q6INSN(SA1_sxtb, "Rd16=sxtb(Rs16)", ATTRIBS(A_SUBINSN),"Sxtb", { RdV= fSXTN(8,32,Rs… 46 Q6INSN(SA1_zxth, "Rd16=zxth(Rs16)", ATTRIBS(A_SUBINSN),"Zxth", { RdV= fZXTN(16,32,R… [all …]
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H A D | branch.idef | 128 Q6INSN(J4_jumpseti,"Rd16=#U6 ; jump #r9:2",ATTRIBS(A_JDIR), "direct unconditional jump and set regi… 131 Q6INSN(J4_jumpsetr,"Rd16=Rs16 ; jump #r9:2",ATTRIBS(A_JDIR), "direct unconditional jump and transfe…
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/dports/editors/hte/ht-e9e63373148da5d7df397d8075740d8c096ecb1d/asm/ |
H A D | avropc.cc | 88 #define Rd16 Rd + 1 macro 91 #define Rd23 Rd16 + 1 186 { "muls", OP_3MASK, 0x0200, {Rd16, Rr16} }, 191 { "cpi", OP_1MASK, 0x3000, {Rd16, K8} }, 192 { "sbci", OP_1MASK, 0x4000, {Rd16, K8} }, 193 { "subi", OP_1MASK, 0x5000, {Rd16, K8} }, 194 { "ori", OP_1MASK, 0x6000, {Rd16, K8} }, 195 { "andi", OP_1MASK, 0x7000, {Rd16, K8} }, 196 { "ldi", OP_1MASK, 0xe000, {Rd16, K8} }, 307 { "ser", OP_8MASK, 0xef0f, {Rd16} },
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 368 bits <4> Rd16; 449 bits <4> Rd16; 507 bits <4> Rd16; 618 bits <4> Rd16; 681 bits <4> Rd16; 1148 bits <4> Rd16; 1586 bits <4> Rd16; 2135 bits <4> Rd16; 2351 bits <4> Rd16; 2525 bits <4> Rd16; [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 402 bits <4> Rd16; 604 bits <4> Rd16; 625 bits <4> Rd16; 675 bits <4> Rd16; 1153 bits <4> Rd16; 1179 bits <4> Rd16; 1464 bits <4> Rd16; 1680 bits <4> Rd16; 2083 bits <4> Rd16; 2183 bits <4> Rd16; [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 402 bits <4> Rd16; 604 bits <4> Rd16; 625 bits <4> Rd16; 675 bits <4> Rd16; 1153 bits <4> Rd16; 1179 bits <4> Rd16; 1464 bits <4> Rd16; 1680 bits <4> Rd16; 2083 bits <4> Rd16; 2183 bits <4> Rd16; [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 368 bits <4> Rd16; 449 bits <4> Rd16; 507 bits <4> Rd16; 618 bits <4> Rd16; 681 bits <4> Rd16; 1148 bits <4> Rd16; 1586 bits <4> Rd16; 2135 bits <4> Rd16; 2351 bits <4> Rd16; 2525 bits <4> Rd16; [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 402 bits <4> Rd16; 604 bits <4> Rd16; 625 bits <4> Rd16; 675 bits <4> Rd16; 1153 bits <4> Rd16; 1179 bits <4> Rd16; 1464 bits <4> Rd16; 1680 bits <4> Rd16; 2083 bits <4> Rd16; 2183 bits <4> Rd16; [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 402 bits <4> Rd16; 604 bits <4> Rd16; 625 bits <4> Rd16; 675 bits <4> Rd16; 1153 bits <4> Rd16; 1179 bits <4> Rd16; 1464 bits <4> Rd16; 1680 bits <4> Rd16; 2083 bits <4> Rd16; 2183 bits <4> Rd16; [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 402 bits <4> Rd16; 604 bits <4> Rd16; 625 bits <4> Rd16; 675 bits <4> Rd16; 1153 bits <4> Rd16; 1179 bits <4> Rd16; 1464 bits <4> Rd16; 1680 bits <4> Rd16; 2083 bits <4> Rd16; 2183 bits <4> Rd16; [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 368 bits <4> Rd16; 449 bits <4> Rd16; 507 bits <4> Rd16; 618 bits <4> Rd16; 681 bits <4> Rd16; 1148 bits <4> Rd16; 1586 bits <4> Rd16; 2135 bits <4> Rd16; 2351 bits <4> Rd16; 2525 bits <4> Rd16; [all …]
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H A D | HexagonDepInstrInfo.td | 25504 "$Rd16 = add(r29,#$Ii)", 25516 "$Rd16 = and($Rs16,#1)", 25527 "if (!p0) $Rd16 = #0", 25556 "if (p0) $Rd16 = #0", 25677 "$Rd16 = add($Rs16,#1)", 25688 "$Rd16 = #$Ii", 25704 "$Rd16 = #$n1", 25715 "$Rd16 = sxtb($Rs16)", 25726 "$Rd16 = sxth($Rs16)", 25737 "$Rd16 = $Rs16", [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 402 bits <4> Rd16; 604 bits <4> Rd16; 625 bits <4> Rd16; 675 bits <4> Rd16; 1153 bits <4> Rd16; 1179 bits <4> Rd16; 1464 bits <4> Rd16; 1680 bits <4> Rd16; 2083 bits <4> Rd16; 2183 bits <4> Rd16; [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 368 bits <4> Rd16; 449 bits <4> Rd16; 507 bits <4> Rd16; 618 bits <4> Rd16; 681 bits <4> Rd16; 1148 bits <4> Rd16; 1586 bits <4> Rd16; 2135 bits <4> Rd16; 2351 bits <4> Rd16; 2525 bits <4> Rd16; [all …]
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 369 bits <4> Rd16; 450 bits <4> Rd16; 508 bits <4> Rd16; 619 bits <4> Rd16; 682 bits <4> Rd16; 1149 bits <4> Rd16; 1587 bits <4> Rd16; 2136 bits <4> Rd16; 2352 bits <4> Rd16; 2526 bits <4> Rd16; [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 958 bits <4> Rd16; 967 bits <4> Rd16; 2532 bits <4> Rd16; 2538 bits <4> Rd16; 2542 bits <4> Rd16; 2566 bits <4> Rd16; 2574 bits <4> Rd16; 2578 bits <4> Rd16; 2588 bits <4> Rd16; 2596 bits <4> Rd16; [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 958 bits <4> Rd16; 967 bits <4> Rd16; 2532 bits <4> Rd16; 2538 bits <4> Rd16; 2542 bits <4> Rd16; 2566 bits <4> Rd16; 2574 bits <4> Rd16; 2578 bits <4> Rd16; 2588 bits <4> Rd16; 2596 bits <4> Rd16; [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 958 bits <4> Rd16; 967 bits <4> Rd16; 2532 bits <4> Rd16; 2538 bits <4> Rd16; 2542 bits <4> Rd16; 2566 bits <4> Rd16; 2574 bits <4> Rd16; 2578 bits <4> Rd16; 2588 bits <4> Rd16; 2596 bits <4> Rd16; [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 958 bits <4> Rd16; 967 bits <4> Rd16; 2532 bits <4> Rd16; 2538 bits <4> Rd16; 2542 bits <4> Rd16; 2566 bits <4> Rd16; 2574 bits <4> Rd16; 2578 bits <4> Rd16; 2588 bits <4> Rd16; 2596 bits <4> Rd16; [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 958 bits <4> Rd16; 967 bits <4> Rd16; 2532 bits <4> Rd16; 2538 bits <4> Rd16; 2542 bits <4> Rd16; 2566 bits <4> Rd16; 2574 bits <4> Rd16; 2578 bits <4> Rd16; 2588 bits <4> Rd16; 2596 bits <4> Rd16; [all …]
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 432 bits <4> Rd16; 505 bits <4> Rd16; 563 bits <4> Rd16; 690 bits <4> Rd16; 753 bits <4> Rd16; 1256 bits <4> Rd16; 1780 bits <4> Rd16; 2426 bits <4> Rd16; 2715 bits <4> Rd16; 2930 bits <4> Rd16; [all …]
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