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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/
H A DVtdReg.c50 UINT32 Reg32; in FlushWriteBuffer() local
56 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in FlushWriteBuffer()
60 } while ((Reg32 & B_GSTS_REG_WBF) != 0); in FlushWriteBuffer()
140 UINT32 Reg32; in EnableDmar() local
152 } while((Reg32 & B_GSTS_REG_RTPS) == 0); in EnableDmar()
181 } while ((Reg32 & B_GSTS_REG_TE) == 0); in EnableDmar()
201 UINT32 Reg32; in DisableDmar() local
218 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in DisableDmar()
228 } while ((Reg32 & B_GSTS_REG_TE) == B_GSTS_REG_TE); in DisableDmar()
233 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in DisableDmar()
[all …]
H A DIntelVTdPmr.c141 UINT32 Reg32; in EnablePmr() local
151 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); in EnablePmr()
152 if (Reg32 == 0xFFFFFFFF) { in EnablePmr()
157 if ((Reg32 & BIT0) == 0) { in EnablePmr()
161 } while((Reg32 & BIT0) == 0); in EnablePmr()
182 UINT32 Reg32; in DisablePmr() local
191 if (Reg32 == 0xFFFFFFFF) { in DisablePmr()
196 if ((Reg32 & BIT0) != 0) { in DisablePmr()
200 } while((Reg32 & BIT0) != 0); in DisablePmr()
371 UINT32 Reg32; in IsPmrEnabled() local
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/
H A DVtdReg.c46 UINT32 Reg32; in FlushWriteBuffer() local
53 } while ((Reg32 & B_GSTS_REG_WBF) != 0); in FlushWriteBuffer()
205 UINT32 Reg32; in DisablePmr() local
217 if ((Reg32 & BIT0) != 0) { in DisablePmr()
221 } while((Reg32 & BIT0) != 0); in DisablePmr()
242 UINT32 Reg32; in EnableDmar() local
317 UINT32 Reg32; in DisableDmar() local
461 UINT32 Reg32; in DumpVtdRegs() local
548 UINT32 Reg32; in DumpVtdIfError() local
554 if (Reg32 != 0) { in DumpVtdIfError()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/
H A DVtdReg.c46 UINT32 Reg32; in FlushWriteBuffer() local
53 } while ((Reg32 & B_GSTS_REG_WBF) != 0); in FlushWriteBuffer()
199 UINT32 Reg32; in DisablePmr() local
211 if ((Reg32 & BIT0) != 0) { in DisablePmr()
215 } while((Reg32 & BIT0) != 0); in DisablePmr()
236 UINT32 Reg32; in EnableDmar() local
311 UINT32 Reg32; in DisableDmar() local
431 UINT32 Reg32; in DumpVtdRegs() local
518 UINT32 Reg32; in DumpVtdIfError() local
524 if (Reg32 != 0) { in DumpVtdIfError()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/
H A DVtdReg.c46 UINT32 Reg32; in FlushWriteBuffer() local
53 } while ((Reg32 & B_GSTS_REG_WBF) != 0); in FlushWriteBuffer()
199 UINT32 Reg32; in DisablePmr() local
211 if ((Reg32 & BIT0) != 0) { in DisablePmr()
215 } while((Reg32 & BIT0) != 0); in DisablePmr()
236 UINT32 Reg32; in EnableDmar() local
311 UINT32 Reg32; in DisableDmar() local
431 UINT32 Reg32; in DumpVtdRegs() local
518 UINT32 Reg32; in DumpVtdIfError() local
524 if (Reg32 != 0) { in DumpVtdIfError()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/
H A DVtdReg.c46 UINT32 Reg32; in FlushWriteBuffer() local
53 } while ((Reg32 & B_GSTS_REG_WBF) != 0); in FlushWriteBuffer()
199 UINT32 Reg32; in DisablePmr() local
211 if ((Reg32 & BIT0) != 0) { in DisablePmr()
215 } while((Reg32 & BIT0) != 0); in DisablePmr()
236 UINT32 Reg32; in EnableDmar() local
311 UINT32 Reg32; in DisableDmar() local
431 UINT32 Reg32; in DumpVtdRegs() local
518 UINT32 Reg32; in DumpVtdIfError() local
524 if (Reg32 != 0) { in DumpVtdIfError()
[all …]
/dports/lang/erlang-runtime22/otp-OTP-22.3.4.24/lib/hipe/x86/
H A Dhipe_x86_encode.erl399 {{reg32,Reg32}} ->
599 {{reg32,Reg32}} ->
600 [16#58 bor Reg32]
615 {{reg32,Reg32}} ->
616 [16#50 bor Reg32];
1144 Reg32 = {reg32,?EAX},
1166 t(OS,'bswap',{Reg32}),
1190 t(OS,'dec',{Reg32}),
1199 t(OS,'inc',{Reg32}),
1246 t(OS,'pop',{Reg32}),
[all …]
/dports/lang/erlang-runtime23/otp-OTP-23.3.4.10/lib/hipe/x86/
H A Dhipe_x86_encode.erl399 {{reg32,Reg32}} ->
599 {{reg32,Reg32}} ->
600 [16#58 bor Reg32]
615 {{reg32,Reg32}} ->
616 [16#50 bor Reg32];
1144 Reg32 = {reg32,?EAX},
1166 t(OS,'bswap',{Reg32}),
1190 t(OS,'dec',{Reg32}),
1199 t(OS,'inc',{Reg32}),
1246 t(OS,'pop',{Reg32}),
[all …]
/dports/lang/erlang-runtime21/otp-OTP-21.3.8.24/lib/hipe/x86/
H A Dhipe_x86_encode.erl399 {{reg32,Reg32}} ->
599 {{reg32,Reg32}} ->
600 [16#58 bor Reg32]
615 {{reg32,Reg32}} ->
616 [16#50 bor Reg32];
1144 Reg32 = {reg32,?EAX},
1166 t(OS,'bswap',{Reg32}),
1190 t(OS,'dec',{Reg32}),
1199 t(OS,'inc',{Reg32}),
1246 t(OS,'pop',{Reg32}),
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/
H A DVtdReg.c48 UINT32 Reg32; in FlushWriteBuffer() local
54 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in FlushWriteBuffer()
57 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in FlushWriteBuffer()
58 } while ((Reg32 & B_GSTS_REG_WBF) != 0); in FlushWriteBuffer()
138 UINT32 Reg32; in EnableDmar() local
149 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in EnableDmar()
150 } while((Reg32 & B_GSTS_REG_RTPS) == 0); in EnableDmar()
179 } while ((Reg32 & B_GSTS_REG_TE) == 0); in EnableDmar()
199 UINT32 Reg32; in DisableDmar() local
214 } while((Reg32 & B_GSTS_REG_RTPS) == 0); in DisableDmar()
[all …]
H A DIntelVTdPmr.c141 UINT32 Reg32; in EnablePmr() local
151 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); in EnablePmr()
152 if (Reg32 == 0xFFFFFFFF) { in EnablePmr()
157 if ((Reg32 & BIT0) == 0) { in EnablePmr()
161 } while((Reg32 & BIT0) == 0); in EnablePmr()
182 UINT32 Reg32; in DisablePmr() local
191 if (Reg32 == 0xFFFFFFFF) { in DisablePmr()
196 if ((Reg32 & BIT0) != 0) { in DisablePmr()
200 } while((Reg32 & BIT0) != 0); in DisablePmr()
371 UINT32 Reg32; in IsPmrEnabled() local
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/
H A DVtdReg.c48 UINT32 Reg32; in FlushWriteBuffer() local
54 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in FlushWriteBuffer()
57 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in FlushWriteBuffer()
58 } while ((Reg32 & B_GSTS_REG_WBF) != 0); in FlushWriteBuffer()
138 UINT32 Reg32; in EnableDmar() local
149 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in EnableDmar()
150 } while((Reg32 & B_GSTS_REG_RTPS) == 0); in EnableDmar()
179 } while ((Reg32 & B_GSTS_REG_TE) == 0); in EnableDmar()
199 UINT32 Reg32; in DisableDmar() local
214 } while((Reg32 & B_GSTS_REG_RTPS) == 0); in DisableDmar()
[all …]
H A DIntelVTdPmr.c141 UINT32 Reg32; in EnablePmr() local
151 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); in EnablePmr()
152 if (Reg32 == 0xFFFFFFFF) { in EnablePmr()
157 if ((Reg32 & BIT0) == 0) { in EnablePmr()
161 } while((Reg32 & BIT0) == 0); in EnablePmr()
182 UINT32 Reg32; in DisablePmr() local
191 if (Reg32 == 0xFFFFFFFF) { in DisablePmr()
196 if ((Reg32 & BIT0) != 0) { in DisablePmr()
200 } while((Reg32 & BIT0) != 0); in DisablePmr()
371 UINT32 Reg32; in IsPmrEnabled() local
[all …]
/dports/devel/vasm/vasm/cpus/x86/
H A Dregisters.h48 {"eax", Reg32|BaseIndex|Acc, 0, 0},
49 {"ecx", Reg32|BaseIndex, 0, 1},
50 {"edx", Reg32|BaseIndex, 0, 2},
51 {"ebx", Reg32|BaseIndex, 0, 3},
52 {"esp", Reg32, 0, 4},
53 {"ebp", Reg32|BaseIndex, 0, 5},
54 {"esi", Reg32|BaseIndex, 0, 6},
55 {"edi", Reg32|BaseIndex, 0, 7},
56 {"r8d", Reg32|BaseIndex, RegRex, 0},
57 {"r9d", Reg32|BaseIndex, RegRex, 1},
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/
H A DVtdReg.c48 UINT32 Reg32; in FlushWriteBuffer() local
54 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in FlushWriteBuffer()
57 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in FlushWriteBuffer()
58 } while ((Reg32 & B_GSTS_REG_WBF) != 0); in FlushWriteBuffer()
138 UINT32 Reg32; in EnableDmar() local
149 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in EnableDmar()
150 } while((Reg32 & B_GSTS_REG_RTPS) == 0); in EnableDmar()
179 } while ((Reg32 & B_GSTS_REG_TE) == 0); in EnableDmar()
199 UINT32 Reg32; in DisableDmar() local
214 } while((Reg32 & B_GSTS_REG_RTPS) == 0); in DisableDmar()
[all …]
H A DIntelVTdPmr.c141 UINT32 Reg32; in EnablePmr() local
151 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); in EnablePmr()
152 if (Reg32 == 0xFFFFFFFF) { in EnablePmr()
157 if ((Reg32 & BIT0) == 0) { in EnablePmr()
161 } while((Reg32 & BIT0) == 0); in EnablePmr()
182 UINT32 Reg32; in DisablePmr() local
191 if (Reg32 == 0xFFFFFFFF) { in DisablePmr()
196 if ((Reg32 & BIT0) != 0) { in DisablePmr()
200 } while((Reg32 & BIT0) != 0); in DisablePmr()
371 UINT32 Reg32; in IsPmrEnabled() local
[all …]
/dports/lang/erlang-runtime22/otp-OTP-22.3.4.24/lib/hipe/amd64/
H A Dhipe_amd64_encode.erl402 {{reg32,Reg32}} ->
403 [rex([{b, Reg32}]), 16#0F, 16#C8 bor (Reg32 band 2#111)];
623 [rex([{b, Reg32}]), 16#B8 bor (Reg32 band 2#111)
1329 Reg32 = {reg32,?EAX},
1351 t(OS,'bswap',{Reg32}),
1352 t(OS,'bt',{RM32,Reg32}),
1375 t(OS,'dec',{Reg32}),
1384 t(OS,'inc',{Reg32}),
1392 t(OS,'lea',{Reg32,EA}),
1431 t(OS,'pop',{Reg32}),
[all …]
/dports/lang/erlang-runtime23/otp-OTP-23.3.4.10/lib/hipe/amd64/
H A Dhipe_amd64_encode.erl402 {{reg32,Reg32}} ->
403 [rex([{b, Reg32}]), 16#0F, 16#C8 bor (Reg32 band 2#111)];
623 [rex([{b, Reg32}]), 16#B8 bor (Reg32 band 2#111)
1329 Reg32 = {reg32,?EAX},
1351 t(OS,'bswap',{Reg32}),
1352 t(OS,'bt',{RM32,Reg32}),
1375 t(OS,'dec',{Reg32}),
1384 t(OS,'inc',{Reg32}),
1392 t(OS,'lea',{Reg32,EA}),
1431 t(OS,'pop',{Reg32}),
[all …]
/dports/lang/erlang-runtime21/otp-OTP-21.3.8.24/lib/hipe/amd64/
H A Dhipe_amd64_encode.erl402 {{reg32,Reg32}} ->
403 [rex([{b, Reg32}]), 16#0F, 16#C8 bor (Reg32 band 2#111)];
623 [rex([{b, Reg32}]), 16#B8 bor (Reg32 band 2#111)
1329 Reg32 = {reg32,?EAX},
1351 t(OS,'bswap',{Reg32}),
1352 t(OS,'bt',{RM32,Reg32}),
1375 t(OS,'dec',{Reg32}),
1384 t(OS,'inc',{Reg32}),
1392 t(OS,'lea',{Reg32,EA}),
1431 t(OS,'pop',{Reg32}),
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/
H A DIntelVTdDmar.c54 UINT32 Reg32; in FlushWriteBuffer() local
60 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in FlushWriteBuffer()
64 } while ((Reg32 & B_GSTS_REG_WBF) != 0); in FlushWriteBuffer()
144 UINT32 Reg32; in EnableDmar() local
156 } while((Reg32 & B_GSTS_REG_RTPS) == 0); in EnableDmar()
185 } while ((Reg32 & B_GSTS_REG_TE) == 0); in EnableDmar()
205 UINT32 Reg32; in DisableDmar() local
222 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in DisableDmar()
232 } while ((Reg32 & B_GSTS_REG_TE) == B_GSTS_REG_TE); in DisableDmar()
237 Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); in DisableDmar()
[all …]
/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/backend/x64/
H A Demit_x64_packed.cpp290 const Xbyak::Reg32 and_a_b = reg_a; in EmitPackedHalvingAddU8()
291 const Xbyak::Reg32 result = reg_a; in EmitPackedHalvingAddU8()
328 const Xbyak::Reg32 and_a_b = reg_a; in EmitPackedHalvingAddU16()
329 const Xbyak::Reg32 result = reg_a; in EmitPackedHalvingAddU16()
353 const Xbyak::Reg32 and_a_b = reg_a; in EmitPackedHalvingAddS8()
354 const Xbyak::Reg32 result = reg_a; in EmitPackedHalvingAddS8()
355 const Xbyak::Reg32 carry = ctx.reg_alloc.ScratchGpr().cvt32(); in EmitPackedHalvingAddS8()
433 const Xbyak::Reg32 carry = ctx.reg_alloc.ScratchGpr().cvt32(); in EmitPackedHalvingSubS8()
517 Xbyak::Reg32 reg_sum, reg_diff; in EmitPackedSubAdd()
545 const Xbyak::Reg32 ge_sum = reg_b_hi; in EmitPackedSubAdd()
[all …]
/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/backend/x64/
H A Demit_x64_packed.cpp290 const Xbyak::Reg32 and_a_b = reg_a; in EmitPackedHalvingAddU8()
291 const Xbyak::Reg32 result = reg_a; in EmitPackedHalvingAddU8()
328 const Xbyak::Reg32 and_a_b = reg_a; in EmitPackedHalvingAddU16()
329 const Xbyak::Reg32 result = reg_a; in EmitPackedHalvingAddU16()
353 const Xbyak::Reg32 and_a_b = reg_a; in EmitPackedHalvingAddS8()
354 const Xbyak::Reg32 result = reg_a; in EmitPackedHalvingAddS8()
355 const Xbyak::Reg32 carry = ctx.reg_alloc.ScratchGpr().cvt32(); in EmitPackedHalvingAddS8()
433 const Xbyak::Reg32 carry = ctx.reg_alloc.ScratchGpr().cvt32(); in EmitPackedHalvingSubS8()
517 Xbyak::Reg32 reg_sum, reg_diff; in EmitPackedSubAdd()
545 const Xbyak::Reg32 ge_sum = reg_b_hi; in EmitPackedSubAdd()
[all …]
/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/backend/x64/
H A Demit_x64_packed.cpp290 const Xbyak::Reg32 and_a_b = reg_a; in EmitPackedHalvingAddU8()
291 const Xbyak::Reg32 result = reg_a; in EmitPackedHalvingAddU8()
328 const Xbyak::Reg32 and_a_b = reg_a; in EmitPackedHalvingAddU16()
329 const Xbyak::Reg32 result = reg_a; in EmitPackedHalvingAddU16()
353 const Xbyak::Reg32 and_a_b = reg_a; in EmitPackedHalvingAddS8()
354 const Xbyak::Reg32 result = reg_a; in EmitPackedHalvingAddS8()
355 const Xbyak::Reg32 carry = ctx.reg_alloc.ScratchGpr().cvt32(); in EmitPackedHalvingAddS8()
433 const Xbyak::Reg32 carry = ctx.reg_alloc.ScratchGpr().cvt32(); in EmitPackedHalvingSubS8()
517 Xbyak::Reg32 reg_sum, reg_diff; in EmitPackedSubAdd()
545 const Xbyak::Reg32 ge_sum = reg_b_hi; in EmitPackedSubAdd()
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Di386-reg.tbl67 eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
68 ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
69 edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
70 ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
71 esp, Reg32, 0, 4, 4, Dw2Inval
72 ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval
73 esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval
74 edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval
75 r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
76 r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
[all …]
/dports/devel/gdb761/gdb-7.6.1/opcodes/
H A Di386-reg.tbl67 eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
68 ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
69 edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
70 ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
71 esp, Reg32, 0, 4, 4, Dw2Inval
72 ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval
73 esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval
74 edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval
75 r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
76 r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
[all …]

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