/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 884 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 918 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1162 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1525 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1626 runEnums(OS, Target, RegBank); in run() 1627 runMCDesc(OS, Target, RegBank); in run() 1628 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 884 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 918 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1162 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1525 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1618 runEnums(OS, Target, RegBank); in run() 1619 runMCDesc(OS, Target, RegBank); in run() 1620 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 209 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 870 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 904 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1150 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1513 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1606 runEnums(OS, Target, RegBank); in run() 1607 runMCDesc(OS, Target, RegBank); in run() 1608 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 881 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 915 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1159 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1523 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1617 runEnums(OS, Target, RegBank); in run() 1620 runMCDesc(OS, Target, RegBank); in run() 1623 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 209 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 870 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 904 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1150 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1513 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1606 runEnums(OS, Target, RegBank); in run() 1607 runMCDesc(OS, Target, RegBank); in run() 1608 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 209 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 870 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 904 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1150 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1513 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1606 runEnums(OS, Target, RegBank); in run() 1607 runMCDesc(OS, Target, RegBank); in run() 1608 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 881 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 915 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1159 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1523 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1617 runEnums(OS, Target, RegBank); in run() 1620 runMCDesc(OS, Target, RegBank); in run() 1623 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 884 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 918 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1162 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1526 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1619 runEnums(OS, Target, RegBank); in run() 1620 runMCDesc(OS, Target, RegBank); in run() 1621 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/llvm80/llvm-8.0.1.src/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 63 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 64 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 210 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 871 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 905 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1151 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1514 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1607 runEnums(OS, Target, RegBank); in run() 1608 runMCDesc(OS, Target, RegBank); in run() 1609 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/llvm70/llvm-7.0.1.src/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 63 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 64 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 210 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 831 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 865 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1115 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1478 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1571 runEnums(OS, Target, RegBank); in run() 1572 runMCDesc(OS, Target, RegBank); in run() 1573 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 874 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 908 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1555 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1649 runEnums(OS, Target, RegBank); in run() 1652 runMCDesc(OS, Target, RegBank); in run() 1655 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 874 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 908 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1554 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1648 runEnums(OS, Target, RegBank); in run() 1651 runMCDesc(OS, Target, RegBank); in run() 1654 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 874 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 908 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1554 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1648 runEnums(OS, Target, RegBank); in run() 1651 runMCDesc(OS, Target, RegBank); in run() 1654 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 874 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 908 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1554 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1648 runEnums(OS, Target, RegBank); in run() 1651 runMCDesc(OS, Target, RegBank); in run() 1654 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 874 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 908 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1554 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1648 runEnums(OS, Target, RegBank); in run() 1651 runMCDesc(OS, Target, RegBank); in run() 1654 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter() 224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure() 874 const auto &Regs = RegBank.getRegisters(); in runMCDesc() 908 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc() 1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader() 1554 printMask(OS, RegBank.CoveringLanes); in runTargetDesc() 1648 runEnums(OS, Target, RegBank); in run() 1651 runMCDesc(OS, Target, RegBank); in run() 1654 runTargetHeader(OS, Target, RegBank); in run() [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local 73 assert(Idx == RegBank.getID() && in verify() 127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints() 129 return &RegBank; in getRegBankFromConstraints() 269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping() 276 PartMapping.RegBank); in hash_value() 520 assert(RegBank && "Register bank not set"); in verify() 530 if (RegBank) in print() 531 OS << *RegBank; in print() 542 if (Part->Length != First->Length || Part->RegBank != First->RegBank) in partsAllUniform() [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local 73 assert(Idx == RegBank.getID() && in verify() 127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints() 129 return &RegBank; in getRegBankFromConstraints() 269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping() 276 PartMapping.RegBank); in hash_value() 520 assert(RegBank && "Register bank not set"); in verify() 530 if (RegBank) in print() 531 OS << *RegBank; in print() 542 if (Part->Length != First->Length || Part->RegBank != First->RegBank) in partsAllUniform() [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local 73 assert(Idx == RegBank.getID() && in verify() 127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints() 129 return &RegBank; in getRegBankFromConstraints() 269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping() 276 PartMapping.RegBank); in hash_value() 520 assert(RegBank && "Register bank not set"); in verify() 530 if (RegBank) in print() 531 OS << *RegBank; in print() 542 if (Part->Length != First->Length || Part->RegBank != First->RegBank) in partsAllUniform() [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local 73 assert(Idx == RegBank.getID() && in verify() 127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints() 129 return &RegBank; in getRegBankFromConstraints() 269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping() 276 PartMapping.RegBank); in hash_value() 519 assert(RegBank && "Register bank not set"); in verify() 529 if (RegBank) in print() 530 OS << *RegBank; in print() 541 if (Part->Length != First->Length || Part->RegBank != First->RegBank) in partsAllUniform() [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local 73 assert(Idx == RegBank.getID() && in verify() 127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints() 129 return &RegBank; in getRegBankFromConstraints() 269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping() 276 PartMapping.RegBank); in hash_value() 519 assert(RegBank && "Register bank not set"); in verify() 529 if (RegBank) in print() 530 OS << *RegBank; in print() 541 if (Part->Length != First->Length || Part->RegBank != First->RegBank) in partsAllUniform() [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local 73 assert(Idx == RegBank.getID() && in verify() 127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints() 129 return &RegBank; in getRegBankFromConstraints() 269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping() 276 PartMapping.RegBank); in hash_value() 520 assert(RegBank && "Register bank not set"); in verify() 530 if (RegBank) in print() 531 OS << *RegBank; in print() 542 if (Part->Length != First->Length || Part->RegBank != First->RegBank) in partsAllUniform() [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local 73 assert(Idx == RegBank.getID() && in verify() 127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints() 129 return &RegBank; in getRegBankFromConstraints() 269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping() 276 PartMapping.RegBank); in hash_value() 520 assert(RegBank && "Register bank not set"); in verify() 530 if (RegBank) in print() 531 OS << *RegBank; in print() 542 if (Part->Length != First->Length || Part->RegBank != First->RegBank) in partsAllUniform() [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local 73 assert(Idx == RegBank.getID() && in verify() 127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints() 129 return &RegBank; in getRegBankFromConstraints() 269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping() 276 PartMapping.RegBank); in hash_value() 519 assert(RegBank && "Register bank not set"); in verify() 529 if (RegBank) in print() 530 OS << *RegBank; in print() 541 if (Part->Length != First->Length || Part->RegBank != First->RegBank) in partsAllUniform() [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local 73 assert(Idx == RegBank.getID() && in verify() 127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints() 129 return &RegBank; in getRegBankFromConstraints() 269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping() 276 PartMapping.RegBank); in hash_value() 519 assert(RegBank && "Register bank not set"); in verify() 529 if (RegBank) in print() 530 OS << *RegBank; in print() 541 if (Part->Length != First->Length || Part->RegBank != First->RegBank) in partsAllUniform() [all …]
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