/dports/math/cgal/CGAL-5.3/include/CGAL/ |
H A D | regular_neighbor_coordinates_2.h | 215 if(lt == Rt::OUTSIDE_AFFINE_HULL || lt == Rt::OUTSIDE_CONVEX_HULL in regular_neighbor_coordinates_vertex_2() 219 if(lt == Rt::VERTEX) in regular_neighbor_coordinates_vertex_2() 245 template <class Rt, class OutputIterator> 257 template <class Rt, class OutputIterator> 279 regular_neighbor_coordinates_2(const Rt& rt, in regular_neighbor_coordinates_2() 304 regular_neighbor_coordinates_2(const Rt& rt, 354 template <class Rt, class OutputIterator> 366 template <class Rt, class OutputIterator> 499 Rt t2; in regular_neighbor_coordinates_2() 527 template <class Rt, class OutputIterator> [all …]
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/dports/devel/openocd/openocd-0.11.0/src/target/ |
H A D | armv8_opcodes.h | 112 #define ARMV8_MRS_DSPSR(Rt) (0xd53b4500 | (Rt)) argument 113 #define ARMV8_MSR_DSPSR(Rt) (0xd51b4500 | (Rt)) argument 114 #define ARMV8_MRS_DLR(Rt) (0xd53b4520 | (Rt)) argument 115 #define ARMV8_MSR_DLR(Rt) (0xd51b4520 | (Rt)) argument 122 #define ARMV8_MRC_DSPSR(Rt) ARMV8_MRC_T1(15, 4, 3, 5, 0, Rt) argument 124 #define ARMV8_MRC_DLR(Rt) ARMV8_MRC_T1(15, 4, 3, 5, 1, Rt) argument 125 #define ARMV8_MCR_DLR(Rt) ARMV8_MCR_T1(15, 4, 3, 5, 1, Rt) argument 182 #define ARMV8_MRS_FPCR(Rt) (0xd53b4400 | (Rt)) argument 183 #define ARMV8_MRS_FPSR(Rt) (0xd53b4420 | (Rt)) argument 184 #define ARMV8_MSR_FPCR(Rt) (0xd51b4400 | (Rt)) argument [all …]
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/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A64/translate/impl/ |
H A D | sys_dc.cpp | 11 v.ir.DataCacheOperationRaised(op, v.X(64, Rt)); in DataCacheInstruction() 15 bool TranslatorVisitor::DC_IVAC(Reg Rt) { in DC_IVAC() argument 19 bool TranslatorVisitor::DC_ISW(Reg Rt) { in DC_ISW() argument 23 bool TranslatorVisitor::DC_CSW(Reg Rt) { in DC_CSW() argument 27 bool TranslatorVisitor::DC_CISW(Reg Rt) { in DC_CISW() argument 31 bool TranslatorVisitor::DC_ZVA(Reg Rt) { in DC_ZVA() argument 32 return DataCacheInstruction(*this, DataCacheOperation::ZeroByVA, Rt); in DC_ZVA() 35 bool TranslatorVisitor::DC_CVAC(Reg Rt) { in DC_CVAC() argument 39 bool TranslatorVisitor::DC_CVAU(Reg Rt) { in DC_CVAU() argument 43 bool TranslatorVisitor::DC_CVAP(Reg Rt) { in DC_CVAP() argument [all …]
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H A D | load_store_exclusive.cpp | 25 if (memop == IR::MemOp::LOAD && pair && Rt == *Rt2) { in ExclusiveSharedDecodeAndOperation() 52 data = v.X(elsize, Rt); in ExclusiveSharedDecodeAndOperation() 61 v.X(64, Rt, v.ir.VectorGetElement(64, data, 0)); in ExclusiveSharedDecodeAndOperation() 64 v.X(32, Rt, v.ir.LeastSignificantWord(data)); in ExclusiveSharedDecodeAndOperation() 67 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in ExclusiveSharedDecodeAndOperation() 110 bool TranslatorVisitor::LDXR(Imm<2> sz, Reg Rn, Reg Rt) { in LDXR() argument 118 bool TranslatorVisitor::LDAXR(Imm<2> sz, Reg Rn, Reg Rt) { in LDAXR() argument 165 const IR::UAny data = v.X(datasize, Rt); in OrderedSharedDecodeAndOperation() 171 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in OrderedSharedDecodeAndOperation() 188 bool TranslatorVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) { in STLR() argument [all …]
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H A D | load_store_register_unprivileged.cpp | 24 const IR::UAny data = v.X(datasize, Rt); in StoreRegister() 86 v.X(regsize, Rt, v.SignExtend(data, regsize)); in LoadRegisterSigned() 88 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in LoadRegisterSigned() 100 return StoreRegister(*this, 8, imm9, Rn, Rt); in STTRB() 104 return StoreRegister(*this, 16, imm9, Rn, Rt); in STTRH() 110 return StoreRegister(*this, datasize, imm9, Rn, Rt); in STTR() 114 return LoadRegister(*this, 8, imm9, Rn, Rt); in LDTRB() 118 return LoadRegister(*this, 16, imm9, Rn, Rt); in LDTRH() 124 return LoadRegister(*this, datasize, imm9, Rn, Rt); in LDTR() 128 return LoadRegisterSigned(*this, 8, opc, imm9, Rn, Rt); in LDTRSB() [all …]
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/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/A64/translate/impl/ |
H A D | sys_dc.cpp | 11 v.ir.DataCacheOperationRaised(op, v.X(64, Rt)); in DataCacheInstruction() 15 bool TranslatorVisitor::DC_IVAC(Reg Rt) { in DC_IVAC() argument 19 bool TranslatorVisitor::DC_ISW(Reg Rt) { in DC_ISW() argument 23 bool TranslatorVisitor::DC_CSW(Reg Rt) { in DC_CSW() argument 27 bool TranslatorVisitor::DC_CISW(Reg Rt) { in DC_CISW() argument 31 bool TranslatorVisitor::DC_ZVA(Reg Rt) { in DC_ZVA() argument 32 return DataCacheInstruction(*this, DataCacheOperation::ZeroByVA, Rt); in DC_ZVA() 35 bool TranslatorVisitor::DC_CVAC(Reg Rt) { in DC_CVAC() argument 39 bool TranslatorVisitor::DC_CVAU(Reg Rt) { in DC_CVAU() argument 43 bool TranslatorVisitor::DC_CVAP(Reg Rt) { in DC_CVAP() argument [all …]
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H A D | load_store_exclusive.cpp | 25 if (memop == IR::MemOp::LOAD && pair && Rt == *Rt2) { in ExclusiveSharedDecodeAndOperation() 52 data = v.X(elsize, Rt); in ExclusiveSharedDecodeAndOperation() 61 v.X(64, Rt, v.ir.VectorGetElement(64, data, 0)); in ExclusiveSharedDecodeAndOperation() 64 v.X(32, Rt, v.ir.LeastSignificantWord(data)); in ExclusiveSharedDecodeAndOperation() 67 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in ExclusiveSharedDecodeAndOperation() 110 bool TranslatorVisitor::LDXR(Imm<2> sz, Reg Rn, Reg Rt) { in LDXR() argument 118 bool TranslatorVisitor::LDAXR(Imm<2> sz, Reg Rn, Reg Rt) { in LDAXR() argument 165 const IR::UAny data = v.X(datasize, Rt); in OrderedSharedDecodeAndOperation() 171 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in OrderedSharedDecodeAndOperation() 188 bool TranslatorVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) { in STLR() argument [all …]
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H A D | load_store_register_unprivileged.cpp | 24 const IR::UAny data = v.X(datasize, Rt); in StoreRegister() 86 v.X(regsize, Rt, v.SignExtend(data, regsize)); in LoadRegisterSigned() 88 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in LoadRegisterSigned() 100 return StoreRegister(*this, 8, imm9, Rn, Rt); in STTRB() 104 return StoreRegister(*this, 16, imm9, Rn, Rt); in STTRH() 110 return StoreRegister(*this, datasize, imm9, Rn, Rt); in STTR() 114 return LoadRegister(*this, 8, imm9, Rn, Rt); in LDTRB() 118 return LoadRegister(*this, 16, imm9, Rn, Rt); in LDTRH() 124 return LoadRegister(*this, datasize, imm9, Rn, Rt); in LDTR() 128 return LoadRegisterSigned(*this, 8, opc, imm9, Rn, Rt); in LDTRSB() [all …]
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/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/A64/translate/impl/ |
H A D | sys_dc.cpp | 11 v.ir.DataCacheOperationRaised(op, v.X(64, Rt)); in DataCacheInstruction() 15 bool TranslatorVisitor::DC_IVAC(Reg Rt) { in DC_IVAC() argument 19 bool TranslatorVisitor::DC_ISW(Reg Rt) { in DC_ISW() argument 23 bool TranslatorVisitor::DC_CSW(Reg Rt) { in DC_CSW() argument 27 bool TranslatorVisitor::DC_CISW(Reg Rt) { in DC_CISW() argument 31 bool TranslatorVisitor::DC_ZVA(Reg Rt) { in DC_ZVA() argument 32 return DataCacheInstruction(*this, DataCacheOperation::ZeroByVA, Rt); in DC_ZVA() 35 bool TranslatorVisitor::DC_CVAC(Reg Rt) { in DC_CVAC() argument 39 bool TranslatorVisitor::DC_CVAU(Reg Rt) { in DC_CVAU() argument 43 bool TranslatorVisitor::DC_CVAP(Reg Rt) { in DC_CVAP() argument [all …]
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H A D | load_store_exclusive.cpp | 25 if (memop == IR::MemOp::LOAD && pair && Rt == *Rt2) { in ExclusiveSharedDecodeAndOperation() 52 data = v.X(elsize, Rt); in ExclusiveSharedDecodeAndOperation() 61 v.X(64, Rt, v.ir.VectorGetElement(64, data, 0)); in ExclusiveSharedDecodeAndOperation() 64 v.X(32, Rt, v.ir.LeastSignificantWord(data)); in ExclusiveSharedDecodeAndOperation() 67 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in ExclusiveSharedDecodeAndOperation() 110 bool TranslatorVisitor::LDXR(Imm<2> sz, Reg Rn, Reg Rt) { in LDXR() argument 118 bool TranslatorVisitor::LDAXR(Imm<2> sz, Reg Rn, Reg Rt) { in LDAXR() argument 165 const IR::UAny data = v.X(datasize, Rt); in OrderedSharedDecodeAndOperation() 171 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in OrderedSharedDecodeAndOperation() 188 bool TranslatorVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) { in STLR() argument [all …]
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H A D | load_store_register_unprivileged.cpp | 24 const IR::UAny data = v.X(datasize, Rt); in StoreRegister() 86 v.X(regsize, Rt, v.SignExtend(data, regsize)); in LoadRegisterSigned() 88 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in LoadRegisterSigned() 100 return StoreRegister(*this, 8, imm9, Rn, Rt); in STTRB() 104 return StoreRegister(*this, 16, imm9, Rn, Rt); in STTRH() 110 return StoreRegister(*this, datasize, imm9, Rn, Rt); in STTR() 114 return LoadRegister(*this, 8, imm9, Rn, Rt); in LDTRB() 118 return LoadRegister(*this, 16, imm9, Rn, Rt); in LDTRH() 124 return LoadRegister(*this, datasize, imm9, Rn, Rt); in LDTR() 128 return LoadRegisterSigned(*this, 8, opc, imm9, Rn, Rt); in LDTRSB() [all …]
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/dports/devel/arm-elf-binutils/binutils-2.37/gas/testsuite/gas/aarch64/ |
H A D | ls64-invalid.l | 2 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x1,\[x1\]' 4 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x5,\[x1\]' 6 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x9,\[x1\]' 8 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x13,\[x1\]' 10 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x17,\[x1\]' 12 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x21,\[x1\]' 14 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x24,\[x1\]' 16 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x26,\[x1\]' 18 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x28,\[x1\]' 22 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x3,\[x1\]' [all …]
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/dports/devel/gnulibiberty/binutils-2.37/gas/testsuite/gas/aarch64/ |
H A D | ls64-invalid.l | 2 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x1,\[x1\]' 4 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x5,\[x1\]' 6 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x9,\[x1\]' 8 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x13,\[x1\]' 10 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x17,\[x1\]' 12 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x21,\[x1\]' 14 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x24,\[x1\]' 16 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x26,\[x1\]' 18 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x28,\[x1\]' 22 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x3,\[x1\]' [all …]
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/dports/devel/binutils/binutils-2.37/gas/testsuite/gas/aarch64/ |
H A D | ls64-invalid.l | 2 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x1,\[x1\]' 4 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x5,\[x1\]' 6 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x9,\[x1\]' 8 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x13,\[x1\]' 10 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x17,\[x1\]' 12 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x21,\[x1\]' 14 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x24,\[x1\]' 16 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x26,\[x1\]' 18 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x28,\[x1\]' 22 .*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x3,\[x1\]' [all …]
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/dports/devel/android-tools-fastboot/platform_system_core-platform-tools-29.0.5/libpixelflinger/codeflinger/ |
H A D | MIPSAssembler.h | 273 void ADDU(int Rd, int Rs, int Rt); 275 void SUBU(int Rd, int Rs, int Rt); 278 void MUL(int Rd, int Rs, int Rt); 294 void SLT(int Rd, int Rs, int Rt); 296 void SLTU(int Rd, int Rs, int Rt); 305 void AND(int Rd, int Rs, int Rt); 307 void OR(int Rd, int Rs, int Rt); 309 void NOR(int Rd, int Rs, int Rt); 311 void XOR(int Rd, int Rs, int Rt); 327 void WSBH(int Rd, int Rt); [all …]
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/dports/devel/android-tools-adb/platform_system_core-android-9.0.0_r3/libpixelflinger/codeflinger/ |
H A D | MIPSAssembler.h | 273 void ADDU(int Rd, int Rs, int Rt); 275 void SUBU(int Rd, int Rs, int Rt); 278 void MUL(int Rd, int Rs, int Rt); 294 void SLT(int Rd, int Rs, int Rt); 296 void SLTU(int Rd, int Rs, int Rt); 305 void AND(int Rd, int Rs, int Rt); 307 void OR(int Rd, int Rs, int Rt); 309 void NOR(int Rd, int Rs, int Rt); 311 void XOR(int Rd, int Rs, int Rt); 327 void WSBH(int Rd, int Rt); [all …]
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/dports/lang/erlang-runtime24/otp-OTP-24.1.7/lib/compiler/src/ |
H A D | core_lint.erl | 201 functions(Fs, Def, Rt, St0) -> 222 body(E, Def, Rt, St0) -> 243 gbody(E, Def, Rt, St0) -> 253 return_match(Rt, 1, St); 266 return_match(Rt, 1, gbody(B, Def, Rt, St1)); 276 _Def, Rt, St) -> 297 Def, Rt, St) -> 298 gbody(E, Def, Rt, St); 335 return_match(Rt, 1, St); 351 body(B, Def, Rt, St1); [all …]
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/dports/lang/erlang-runtime23/otp-OTP-23.3.4.10/lib/compiler/src/ |
H A D | core_lint.erl | 200 functions(Fs, Def, Rt, St0) -> 221 body(E, Def, Rt, St0) -> 242 gbody(E, Def, Rt, St0) -> 252 return_match(Rt, 1, St); 265 return_match(Rt, 1, gbody(B, Def, Rt, St1)); 275 _Def, Rt, St) -> 296 Def, Rt, St) -> 297 gbody(E, Def, Rt, St); 334 return_match(Rt, 1, St); 350 body(B, Def, Rt, St1); [all …]
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/dports/lang/erlang-wx/otp-OTP-24.1.7/lib/compiler/src/ |
H A D | core_lint.erl | 201 functions(Fs, Def, Rt, St0) -> 222 body(E, Def, Rt, St0) -> 243 gbody(E, Def, Rt, St0) -> 253 return_match(Rt, 1, St); 266 return_match(Rt, 1, gbody(B, Def, Rt, St1)); 276 _Def, Rt, St) -> 297 Def, Rt, St) -> 298 gbody(E, Def, Rt, St); 335 return_match(Rt, 1, St); 351 body(B, Def, Rt, St1); [all …]
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/dports/lang/erlang-java/otp-OTP-24.1.7/lib/compiler/src/ |
H A D | core_lint.erl | 201 functions(Fs, Def, Rt, St0) -> 222 body(E, Def, Rt, St0) -> 243 gbody(E, Def, Rt, St0) -> 253 return_match(Rt, 1, St); 266 return_match(Rt, 1, gbody(B, Def, Rt, St1)); 276 _Def, Rt, St) -> 297 Def, Rt, St) -> 298 gbody(E, Def, Rt, St); 335 return_match(Rt, 1, St); 351 body(B, Def, Rt, St1); [all …]
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/dports/lang/erlang/otp-OTP-24.1.7/lib/compiler/src/ |
H A D | core_lint.erl | 201 functions(Fs, Def, Rt, St0) -> 222 body(E, Def, Rt, St0) -> 243 gbody(E, Def, Rt, St0) -> 253 return_match(Rt, 1, St); 266 return_match(Rt, 1, gbody(B, Def, Rt, St1)); 276 _Def, Rt, St) -> 297 Def, Rt, St) -> 298 gbody(E, Def, Rt, St); 335 return_match(Rt, 1, St); 351 body(B, Def, Rt, St1); [all …]
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/dports/lang/erlang-runtime22/otp-OTP-22.3.4.24/lib/compiler/src/ |
H A D | core_lint.erl | 220 body(E, Def, Rt, St0) -> 221 St1 = expr(E, Def, Rt, St0), 241 gbody(E, Def, Rt, St0) -> 251 return_match(Rt, 1, St); 264 return_match(Rt, 1, gbody(B, Def, Rt, St1)); 274 _Def, Rt, St) -> 289 Def, Rt, St) -> 290 gbody(E, Def, Rt, St); 327 return_match(Rt, 1, St); 343 body(B, Def, Rt, St1); [all …]
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/dports/lang/erlang-runtime21/otp-OTP-21.3.8.24/lib/compiler/src/ |
H A D | core_lint.erl | 220 body(E, Def, Rt, St0) -> 221 St1 = expr(E, Def, Rt, St0), 241 gbody(E, Def, Rt, St0) -> 251 return_match(Rt, 1, St); 264 return_match(Rt, 1, gbody(B, Def, Rt, St1)); 274 _Def, Rt, St) -> 289 Def, Rt, St) -> 290 gbody(E, Def, Rt, St); 327 return_match(Rt, 1, St); 343 body(B, Def, Rt, St1); [all …]
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/dports/emulators/dolphin-emu/dolphin-3152428/Source/Core/Common/ |
H A D | Arm64Emitter.cpp | 532 Rt = DecodeReg(Rt); in EncodeCompareBranchInst() 549 Rt = DecodeReg(Rt); in EncodeTestBranchInst() 703 Rt = DecodeReg(Rt); in EncodeLoadRegisterInst() 715 Rt = DecodeReg(Rt); in EncodeLoadStoreExcInst() 745 Rt = DecodeReg(Rt); in EncodeLoadStorePairedInst() 760 Rt = DecodeReg(Rt); in EncodeLoadStoreIndexedInst() 781 Rt = DecodeReg(Rt); in EncodeLoadStoreIndexedInst() 809 Rt = DecodeReg(Rt); in EncodeLoadStoreRegisterOffset() 876 Rt = DecodeReg(Rt); in EncodeLoadStorePair() 894 Rt = DecodeReg(Rt); in EncodeLoadStoreUnscaled() [all …]
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/dports/emulators/ppsspp-qt5/ppsspp-1.12.3/Common/ |
H A D | Arm64Emitter.cpp | 495 Rt = DecodeReg(Rt); 511 Rt = DecodeReg(Rt); 659 Rt = DecodeReg(Rt); 671 Rt = DecodeReg(Rt); 700 Rt = DecodeReg(Rt); 715 Rt = DecodeReg(Rt); 741 Rt = DecodeReg(Rt); 768 Rt = DecodeReg(Rt); 832 Rt = DecodeReg(Rt); 850 Rt = DecodeReg(Rt); [all …]
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