| /dports/lang/micropython/micropython-1.17/ports/stm32/ |
| H A D | sdram.c | 263 FMC_SDRAM_DEVICE->SDCMR |= (FMC_SDRAM_CMD_SELFREFRESH_MODE | // Command Mode in sdram_enter_low_power()
273 FMC_SDRAM_DEVICE->SDCMR |= (FMC_SDRAM_CMD_NORMAL_MODE | // Command Mode in sdram_leave_low_power()
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F4xx_StdPeriph_Driver/src/ |
| H A D | stm32f4xx_fmc.c | 915 FMC_Bank5_6->SDCMR = 0x00000000; in FMC_SDRAMDeInit()
1100 FMC_Bank5_6->SDCMR = tmpr; in FMC_SDRAMCmdConfig()
1156 FMC_Bank5_6->SDCMR |= (FMC_Number << 5); in FMC_SetAutoRefresh_Number()
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F4xx_StdPeriph_Driver/src/ |
| H A D | stm32f4xx_fmc.c | 915 FMC_Bank5_6->SDCMR = 0x00000000; in FMC_SDRAMDeInit()
1100 FMC_Bank5_6->SDCMR = tmpr; in FMC_SDRAMCmdConfig()
1156 FMC_Bank5_6->SDCMR |= (FMC_Number << 5); in FMC_SetAutoRefresh_Number()
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| /dports/science/nwchem-data/nwchem-7.0.2-release/src/lucia/ |
| H A D | testcase.reference.output | 1810 SDCMR 5664 0.00 0.00
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| /dports/science/nwchem/nwchem-7b21660b82ebd85ef659f6fba7e1e73433b0bd0a/src/lucia/ |
| H A D | testcase.reference.output | 1810 SDCMR 5664 0.00 0.00
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| /dports/lang/fpc-source/fpc-3.2.2/rtl/embedded/arm/ |
| H A D | stm32f446xx.pp | 332 SDCMR : longword; // SDRAM Command Mode register
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| H A D | stm32f429xx.pp | 438 SDCMR : longword; // SDRAM Command Mode register
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| H A D | stm32f745.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
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| H A D | stm32f746.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
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| H A D | stm32f756.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
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| /dports/lang/fpc/fpc-3.2.2/rtl/embedded/arm/ |
| H A D | stm32f446xx.pp | 332 SDCMR : longword; // SDRAM Command Mode register
|
| H A D | stm32f429xx.pp | 438 SDCMR : longword; // SDRAM Command Mode register
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| H A D | stm32f745.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
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| H A D | stm32f746.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
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| H A D | stm32f756.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
|
| /dports/lang/fpc-utils/fpc-3.2.2/rtl/embedded/arm/ |
| H A D | stm32f446xx.pp | 332 SDCMR : longword; // SDRAM Command Mode register
|
| H A D | stm32f429xx.pp | 438 SDCMR : longword; // SDRAM Command Mode register
|
| H A D | stm32f745.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
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| H A D | stm32f746.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
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| H A D | stm32f756.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
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| /dports/editors/fpc-ide/fpc-3.2.2/rtl/embedded/arm/ |
| H A D | stm32f446xx.pp | 332 SDCMR : longword; // SDRAM Command Mode register
|
| H A D | stm32f429xx.pp | 438 SDCMR : longword; // SDRAM Command Mode register
|
| H A D | stm32f745.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
|
| H A D | stm32f746.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
|
| H A D | stm32f756.pp | 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *)
|