/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/X86/GlobalISel/ |
H A D | x86_64-select-fcmp.mir | 212 ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags 213 ; CHECK: $al = COPY [[SETAr]] 288 ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags 289 ; CHECK: $al = COPY [[SETAr]] 748 ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags 749 ; CHECK: $al = COPY [[SETAr]] 824 ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags 825 ; CHECK: $al = COPY [[SETAr]]
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H A D | select-cmp.mir | 257 ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags 258 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAr]], %subreg.sub_8bit
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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/X86/ |
H A D | flags-copy-lowering.mir | 122 ; CHECK: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 178 ; CHECK: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 233 ; CHECK: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 244 %3:gr8 = SETAr implicit $eflags 276 ; CHECK: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 604 ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 678 ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 827 ; CHECK: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 965 %2:gr8 = SETAr implicit $eflags 969 ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags
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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/X86/ |
H A D | flags-copy-lowering.mir | 122 ; CHECK: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 178 ; CHECK: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 233 ; CHECK: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 244 %3:gr8 = SETAr implicit $eflags 276 ; CHECK: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 604 ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 678 ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 827 ; CHECK: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags 965 %2:gr8 = SETAr implicit $eflags 969 ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/X86/ |
H A D | X86FixupSetCC.cpp | 82 case X86::SETAr: in isSetCCr()
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/X86/ |
H A D | X86FixupSetCC.cpp | 82 case X86::SETAr:
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H A D | X86ISelDAGToDAG.cpp | 2103 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/X86/GlobalISel/ |
H A D | select-cmp.mir | 257 ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags 258 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAr]], %subreg.sub_8bit
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/dports/lang/smalltalk/smalltalk-3.2.5/lightning/i386/ |
H A D | core-i386.h | 293 #define jit_gtr_ui(d, s1, s2) jit_bool_r((d), (s1), (s2), SETAr ) 304 #define jit_gti_ui(d, rs, is) jit_bool_i0((d), (rs), (is), SETAr, SETNEr )
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H A D | asm-i386.h | 798 #define SETAr(RD) SETCCir(0x7,RD) macro
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/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 899 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; in X86SelectCmp() 901 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break; in X86SelectCmp() 914 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; in X86SelectCmp()
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H A D | X86ISelDAGToDAG.cpp | 1517 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr: in HasNoSignedComparisonUses()
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/dports/lang/racket-minimal/racket-8.3/src/bc/src/lightning/i386/ |
H A D | core.h | 530 #define jit_gtr_ui(d, s1, s2) jit_bool_r((d), (s1), (s2), SETAr ) 541 #define jit_gti_ui(d, rs, is) jit_bool_i0((d), (rs), (is), SETAr, SETNEr )
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/dports/lang/racket/racket-8.3/src/bc/src/lightning/i386/ |
H A D | core.h | 530 #define jit_gtr_ui(d, s1, s2) jit_bool_r((d), (s1), (s2), SETAr ) 541 #define jit_gti_ui(d, rs, is) jit_bool_i0((d), (rs), (is), SETAr, SETNEr )
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/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/ |
H A D | X86GenInstrNames.inc | 2232 SETAr = 2219,
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/dports/devel/capstone4/capstone-4.0.2/arch/X86/ |
H A D | X86GenAsmWriter1_reduce.inc | 1362 4168U, // SETAr 3080 0U, // SETAr
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/dports/devel/py-capstone/capstone-4.0.1/src/arch/X86/ |
H A D | X86GenAsmWriter1_reduce.inc | 1362 4168U, // SETAr 3080 0U, // SETAr
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/dports/devel/redasm/REDasm-2.1.1/LibREDasm/depends/capstone/arch/X86/ |
H A D | X86GenAsmWriter1_reduce.inc | 1362 4168U, // SETAr 3080 0U, // SETAr
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/dports/emulators/qemu/qemu-6.2.0/capstone/arch/X86/ |
H A D | X86GenAsmWriter1_reduce.inc | 1754 4168U, // SETAr
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/dports/emulators/qemu60/qemu-6.0.0/capstone/arch/X86/ |
H A D | X86GenAsmWriter1_reduce.inc | 1754 4168U, // SETAr
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/dports/emulators/gngeo/gngeo-gngeo_0.8/src/generator68k/ccg/ |
H A D | asm-i386.h | 876 #define SETAr(RD) SETCCir(0x7,RD) macro
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/dports/emulators/qemu5/qemu-5.2.0/capstone/arch/X86/ |
H A D | X86GenAsmWriter1_reduce.inc | 1754 4168U, // SETAr
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/dports/devel/xelfviewer/XELFViewer-0.03/XCapstone/3rdparty/Capstone/src/arch/X86/ |
H A D | X86GenAsmWriter1_reduce.inc | 1754 4168U, // SETAr
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/dports/devel/capstone3/capstone-3.0.5/arch/X86/ |
H A D | X86GenAsmWriter1_reduce.inc | 1329 4137U, // SETAr
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/dports/emulators/qemu42/qemu-4.2.1/capstone/arch/X86/ |
H A D | X86GenAsmWriter1_reduce.inc | 1329 4137U, // SETAr
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