/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/d30v/ |
H A D | ic-d30v | 43 # OBSOLETE compute:IMM_6S:imm:signed32:SEXT32(IMM_6S, 32 - 6) 56 # OBSOLETE compute:IMM_18S:pcdisp:signed32:(SEXT32(IMM_18S, 32 - 18) << 3) 59 # OBSOLETE compute:IMM_12S:pcdisp:signed32:(SEXT32(IMM_12S, 32 - 12) << 3) 74 # OBSOLETE compute:SRC_6:src:unsigned32:(XX == 2 ? SEXT32(SRC_6, 32 - 6) : GPR[SRC_6])
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H A D | d30v-insns | 1073 # OBSOLETE WRITE32_QUEUE (&GPR[ra + 0], SEXT32(EXTRACTED32(mem, 0, 15), 16)); 1074 # OBSOLETE WRITE32_QUEUE (&GPR[ra + 1], SEXT32(EXTRACTED32(mem, 16, 31), 16)); 1424 # OBSOLETE value = SEXT32(VL2_4(rb), 16) * SEXT32(VL2_4(src), 16); 1427 # OBSOLETE value = SEXT32(VL2_4(rb), 16) * SEXT32(VH2_4(src), 16); 1430 # OBSOLETE value = SEXT32(VH2_4(rb), 16) * SEXT32(VL2_4(src), 16); 1433 # OBSOLETE value = SEXT32(VH2_4(rb), 16) * SEXT32(VH2_4(src), 16);
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/d30v/ |
H A D | ic-d30v | 43 # OBSOLETE compute:IMM_6S:imm:signed32:SEXT32(IMM_6S, 32 - 6) 56 # OBSOLETE compute:IMM_18S:pcdisp:signed32:(SEXT32(IMM_18S, 32 - 18) << 3) 59 # OBSOLETE compute:IMM_12S:pcdisp:signed32:(SEXT32(IMM_12S, 32 - 12) << 3) 74 # OBSOLETE compute:SRC_6:src:unsigned32:(XX == 2 ? SEXT32(SRC_6, 32 - 6) : GPR[SRC_6])
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H A D | d30v-insns | 1073 # OBSOLETE WRITE32_QUEUE (&GPR[ra + 0], SEXT32(EXTRACTED32(mem, 0, 15), 16)); 1074 # OBSOLETE WRITE32_QUEUE (&GPR[ra + 1], SEXT32(EXTRACTED32(mem, 16, 31), 16)); 1424 # OBSOLETE value = SEXT32(VL2_4(rb), 16) * SEXT32(VL2_4(src), 16); 1427 # OBSOLETE value = SEXT32(VL2_4(rb), 16) * SEXT32(VH2_4(src), 16); 1430 # OBSOLETE value = SEXT32(VH2_4(rb), 16) * SEXT32(VL2_4(src), 16); 1433 # OBSOLETE value = SEXT32(VH2_4(rb), 16) * SEXT32(VH2_4(src), 16);
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/dports/devel/avr-gdb/gdb-7.3.1/sim/common/ |
H A D | sim-bits.h | 591 #define SEXT32 MSSEXT32 macro 597 #define SEXT32 LSSEXT32 macro
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/dports/devel/gdb761/gdb-7.6.1/sim/common/ |
H A D | sim-bits.h | 591 #define SEXT32 MSSEXT32 macro 597 #define SEXT32 LSSEXT32 macro
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/common/ |
H A D | sim-bits.h | 593 #define SEXT32 MSSEXT32 macro 599 #define SEXT32 LSSEXT32 macro
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/common/ |
H A D | sim-bits.h | 593 #define SEXT32 MSSEXT32 macro 599 #define SEXT32 LSSEXT32 macro
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/v850/ |
H A D | v850.igen | 29 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1) 32 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 2… 34 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
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/dports/devel/avr-gdb/gdb-7.3.1/sim/v850/ |
H A D | v850.igen | 29 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1) 32 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 2… 34 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/v850/ |
H A D | v850.igen | 29 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1) 32 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 2… 34 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
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/dports/devel/avr-gdb/gdb-7.3.1/sim/cr16/ |
H A D | cr16_sim.h | 421 #define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000) macro
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/dports/devel/avr-gdb/gdb-7.3.1/sim/testsuite/common/ |
H A D | bits-tst.c | 127 return SEXT32 (val, col); in calc()
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/dports/devel/gdb761/gdb-7.6.1/sim/testsuite/common/ |
H A D | bits-tst.c | 127 return SEXT32 (val, col); in calc()
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/dports/devel/gdb761/gdb-7.6.1/sim/cr16/ |
H A D | cr16_sim.h | 421 #define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000) macro
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/testsuite/common/ |
H A D | bits-tst.c | 127 return SEXT32 (val, col); in calc()
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/testsuite/common/ |
H A D | bits-tst.c | 127 return SEXT32 (val, col); in calc()
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/dports/emulators/simh/simh-3.9.0_5/Interdata/ |
H A D | id32_cpu.c | 194 #define SEXT32(x) (((x) & SIGN32)? ((int32) ((x) | ~0x7FFFFFFF)): \ macro 1113 rslt = (SEXT32 (R[r1]) >> opnd) & DMASK32; /* result */ in sim_instr() 1288 st = SEXT32 (R[r1]) / SEXT16 (opnd); /* quotient */ in sim_instr() 1289 sr = SEXT32 (R[r1]) % SEXT16 (opnd); /* remainder */ in sim_instr()
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/dports/devel/avr-gdb/gdb-7.3.1/sim/d10v/ |
H A D | d10v_sim.h | 412 #define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000)) macro
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/dports/devel/gdb761/gdb-7.6.1/sim/d10v/ |
H A D | d10v_sim.h | 412 #define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000)) macro
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/d10v/ |
H A D | d10v_sim.h | 412 #define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000)) macro
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/d10v/ |
H A D | d10v_sim.h | 412 #define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000)) macro
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/dports/devel/gdb761/gdb-7.6.1/sim/v850/ |
H A D | v850.igen | 42 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1) 45 :cache:::unsigned:disp17:d,ddddddddddddddd:SEXT32 (((d <<16) + (ddddddddddddddd << 1)), 17 - 1) 46 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 2… 47 :cache:::unsigned:disp23:ddddddd,dddddddddddddddd: SEXT32 ((ddddddd) + (dddddddddddddddd << 7), 23 … 48 :cache:::unsigned:disp23:dddddd,dddddddddddddddd: SEXT32 ((dddddd << 1) + (dddddddddddddddd << 7), … 50 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/sh/ |
H A D | interp.c | 768 #define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1) 770 #define SEXT32(x) ((int) (x)) macro 772 #define SIGN32(x) (SEXT32 (x) >> 31)
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/sh/ |
H A D | interp.c | 768 #define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1) 770 #define SEXT32(x) ((int) (x)) macro 772 #define SIGN32(x) (SEXT32 (x) >> 31)
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