| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/mn10200/ |
| H A D | simops.c | 29 State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff);
102 + SEXT8 (insn & 0xff))));
153 + SEXT8 (insn & 0xff))));
340 + SEXT8 (insn & 0xff))));
391 = SEXT8 (load_byte ((State.regs[REG_A0 + REG1_8 (insn)]
392 + SEXT8 (insn & 0xff))));
418 = SEXT8 (load_byte ((State.regs[REG_A0 + REG1 (insn)]
719 imm = TRUNC (SEXT8 (insn & 0xff));
815 imm = TRUNC (SEXT8 (insn & 0xff));
941 imm = SEXT8 (insn & 0xff);
[all …]
|
| H A D | mn10200_sim.h | 114 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/mn10200/ |
| H A D | simops.c | 29 State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff);
102 + SEXT8 (insn & 0xff))));
153 + SEXT8 (insn & 0xff))));
340 + SEXT8 (insn & 0xff))));
391 = SEXT8 (load_byte ((State.regs[REG_A0 + REG1_8 (insn)]
392 + SEXT8 (insn & 0xff))));
418 = SEXT8 (load_byte ((State.regs[REG_A0 + REG1 (insn)]
719 imm = TRUNC (SEXT8 (insn & 0xff));
815 imm = TRUNC (SEXT8 (insn & 0xff));
941 imm = SEXT8 (insn & 0xff);
[all …]
|
| H A D | mn10200_sim.h | 114 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80) macro
|
| /dports/emulators/simh-hpdoc/simh-hpdoc-3.11.0/SCP/HP3000/ |
| H A D | hp3000_cpu_cis.c | 1624 … RD = RD - 1 + SEXT8 (operand) & R_MASK; /* then add the signed displacement to the offset */ in edit()
1632 … RC = RC - SEXT8 (operand) & R_MASK; /* subtract the signed displacement from the offset */ in edit()
1638 … RB = RB - SEXT8 (operand) & R_MASK; /* subtract the signed displacement from the offset */ in edit()
1763 …RD = RD - 1 - SEXT8 (byte) & R_MASK; /* then subtract the signed displacement from the offset… in edit()
|
| H A D | hp3000_defs.h | 571 #define SEXT8(x) (int32) ((x) & D8_SIGN ? (x) | ~D8_MASK : (x)) macro
|
| /dports/emulators/simh-hp3000/simh-hp3000-3.11.0.10/SCP/HP3000/ |
| H A D | hp3000_cpu_cis.c | 1800 … RD = RD - 1 + SEXT8 (operand) & R_MASK; /* then add the signed displacement to the offset */ in edit()
1808 … RC = RC - SEXT8 (operand) & R_MASK; /* subtract the signed displacement from the offset */ in edit()
1814 … RB = RB - SEXT8 (operand) & R_MASK; /* subtract the signed displacement from the offset */ in edit()
1939 …RD = RD - 1 - SEXT8 (byte) & R_MASK; /* then subtract the signed displacement from the offset… in edit()
|
| H A D | hp3000_defs.h | 563 #define SEXT8(x) (int32) ((x) & D8_SIGN ? (x) | ~D8_MASK : (x)) macro
|
| /dports/devel/avr-gdb/gdb-7.3.1/sim/d10v/ |
| H A D | simops.c | 296 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
438 (uint16)SEXT8(OP[i]));
858 JMP( PC + SEXT8 (OP[0])); in OP_4900()
888 JMP (PC + SEXT8 (OP[0])); in OP_4800()
907 JMP (PC + SEXT8 (OP[0])); in OP_4A00()
927 JMP (PC + SEXT8 (OP[0])); in OP_4B00()
1518 tmp = SEXT8 (RB (OP[1] + GPR (OP[2]))); in OP_38000000()
1529 tmp = SEXT8 (RB (GPR (OP[1]))); in OP_7000()
1968 tmp = SEXT8 (GPR (OP[1]) & 0xff); in OP_5400()
|
| /dports/devel/gdb761/gdb-7.6.1/sim/d10v/ |
| H A D | simops.c | 296 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
438 (uint16)SEXT8(OP[i]));
858 JMP( PC + SEXT8 (OP[0])); in OP_4900()
888 JMP (PC + SEXT8 (OP[0])); in OP_4800()
907 JMP (PC + SEXT8 (OP[0])); in OP_4A00()
927 JMP (PC + SEXT8 (OP[0])); in OP_4B00()
1518 tmp = SEXT8 (RB (OP[1] + GPR (OP[2]))); in OP_38000000()
1529 tmp = SEXT8 (RB (GPR (OP[1]))); in OP_7000()
1968 tmp = SEXT8 (GPR (OP[1]) & 0xff); in OP_5400()
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/d10v/ |
| H A D | simops.c | 296 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
438 (uint16)SEXT8(OP[i]));
858 JMP( PC + SEXT8 (OP[0])); in OP_4900()
888 JMP (PC + SEXT8 (OP[0])); in OP_4800()
907 JMP (PC + SEXT8 (OP[0])); in OP_4A00()
927 JMP (PC + SEXT8 (OP[0])); in OP_4B00()
1518 tmp = SEXT8 (RB (OP[1] + GPR (OP[2]))); in OP_38000000()
1529 tmp = SEXT8 (RB (GPR (OP[1]))); in OP_7000()
1968 tmp = SEXT8 (GPR (OP[1]) & 0xff); in OP_5400()
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/d10v/ |
| H A D | simops.c | 296 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
438 (uint16)SEXT8(OP[i]));
858 JMP( PC + SEXT8 (OP[0])); in OP_4900()
888 JMP (PC + SEXT8 (OP[0])); in OP_4800()
907 JMP (PC + SEXT8 (OP[0])); in OP_4A00()
927 JMP (PC + SEXT8 (OP[0])); in OP_4B00()
1518 tmp = SEXT8 (RB (OP[1] + GPR (OP[2]))); in OP_38000000()
1529 tmp = SEXT8 (RB (GPR (OP[1]))); in OP_7000()
1968 tmp = SEXT8 (GPR (OP[1]) & 0xff); in OP_5400()
|
| /dports/devel/avr-gdb/gdb-7.3.1/sim/common/ |
| H A D | sim-bits.h | 589 #define SEXT8 MSSEXT8 macro
595 #define SEXT8 LSSEXT8 macro
|
| /dports/devel/gdb761/gdb-7.6.1/sim/common/ |
| H A D | sim-bits.h | 589 #define SEXT8 MSSEXT8 macro
595 #define SEXT8 LSSEXT8 macro
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/common/ |
| H A D | sim-bits.h | 591 #define SEXT8 MSSEXT8 macro
597 #define SEXT8 LSSEXT8 macro
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/common/ |
| H A D | sim-bits.h | 591 #define SEXT8 MSSEXT8 macro
597 #define SEXT8 LSSEXT8 macro
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 86 unsigned SEXT8; member
273 STORE_OPCODE(SEXT8, SXTB); in OpcodeCache()
299 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16; in selectSimpleExtOpc()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 91 unsigned SEXT8; member
303 STORE_OPCODE(SEXT8, SXTB); in OpcodeCache()
347 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16; in selectSimpleExtOpc()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 91 unsigned SEXT8; member
305 STORE_OPCODE(SEXT8, SXTB); in OpcodeCache()
349 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16; in selectSimpleExtOpc()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 91 unsigned SEXT8; member
303 STORE_OPCODE(SEXT8, SXTB); in OpcodeCache()
347 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16; in selectSimpleExtOpc()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 91 unsigned SEXT8; member
303 STORE_OPCODE(SEXT8, SXTB); in OpcodeCache()
347 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16; in selectSimpleExtOpc()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 91 unsigned SEXT8; member
303 STORE_OPCODE(SEXT8, SXTB); in OpcodeCache()
347 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16; in selectSimpleExtOpc()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 91 unsigned SEXT8; member
305 STORE_OPCODE(SEXT8, SXTB); in OpcodeCache()
349 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16; in selectSimpleExtOpc()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 91 unsigned SEXT8; member
303 STORE_OPCODE(SEXT8, SXTB); in OpcodeCache()
347 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16; in selectSimpleExtOpc()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 91 unsigned SEXT8; member
303 STORE_OPCODE(SEXT8, SXTB); in OpcodeCache()
347 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16; in selectSimpleExtOpc()
|