Searched refs:SFPP0_RS0 (Results 1 – 4 of 4) sorted by relevance
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
| H A D | x300_core.v | 49 inout SFPP0_RS0, port
311 .SFPP0_RS0(SFPP0_RS0), .SFPP0_RS1(SFPP0_RS1),
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| H A D | x300.v | 225 output SFPP0_RS0, // These are actually open drain outputs port
1357 .SFPP0_RxLOS(SFPP0_RxLOS), .SFPP0_RS1(SFPP0_RS1), .SFPP0_RS0(SFPP0_RS0),
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| H A D | bus_int.v | 45 input SFPP0_ModAbs, input SFPP0_TxFault, input SFPP0_RxLOS, inout SFPP0_RS0, inout SFPP0_RS1, port
597 assign SFPP0_RS0 = sfpp0_ctrl[0] ? 1'b0 : 1'bz;
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| H A D | x300.xdc | 597 set_property PACKAGE_PIN W22 [get_ports SFPP0_RS0]
598 set_property IOSTANDARD LVCMOS33 [get_ports SFPP0_RS0]
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