/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 160 SMINV_PRED, enumerator
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H A D | AArch64SVEInstrInfo.td | 61 def AArch64sminv_pred : SDNode<"AArch64ISD::SMINV_PRED", SDT_AArch64Reduce>;
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 160 SMINV_PRED, enumerator
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H A D | AArch64SVEInstrInfo.td | 61 def AArch64sminv_pred : SDNode<"AArch64ISD::SMINV_PRED", SDT_AArch64Reduce>;
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 160 SMINV_PRED, enumerator
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H A D | AArch64SVEInstrInfo.td | 61 def AArch64sminv_pred : SDNode<"AArch64ISD::SMINV_PRED", SDT_AArch64Reduce>;
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 204 SMINV_PRED, enumerator
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 204 SMINV_PRED, enumerator
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 243 SMINV_PRED, enumerator
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H A D | AArch64ISelLowering.cpp | 1723 MAKE_CASE(AArch64ISD::SMINV_PRED) in getTargetNodeName() 9963 return LowerReductionToSVE(AArch64ISD::SMINV_PRED, Op, DAG); in LowerVECREDUCE() 13051 return combineSVEReductionInt(N, AArch64ISD::SMINV_PRED, DAG); in performIntrinsicCombine()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 245 SMINV_PRED, enumerator
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H A D | AArch64ISelLowering.cpp | 1850 MAKE_CASE(AArch64ISD::SMINV_PRED) in getTargetNodeName() 10378 return LowerReductionToSVE(AArch64ISD::SMINV_PRED, Op, DAG); in LowerVECREDUCE() 13623 return combineSVEReductionInt(N, AArch64ISD::SMINV_PRED, DAG); in performIntrinsicCombine()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 245 SMINV_PRED, enumerator
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 257 SMINV_PRED, enumerator
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H A D | AArch64ISelLowering.cpp | 2022 MAKE_CASE(AArch64ISD::SMINV_PRED) in getTargetNodeName() 10973 return LowerReductionToSVE(AArch64ISD::SMINV_PRED, Op, DAG); in LowerVECREDUCE() 14399 return combineSVEReductionInt(N, AArch64ISD::SMINV_PRED, DAG); in performIntrinsicCombine() 16526 case AArch64ISD::SMINV_PRED: in isLanes1toNKnownZero()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 257 SMINV_PRED, enumerator
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H A D | AArch64ISelLowering.cpp | 2022 MAKE_CASE(AArch64ISD::SMINV_PRED) in getTargetNodeName() 10973 return LowerReductionToSVE(AArch64ISD::SMINV_PRED, Op, DAG); in LowerVECREDUCE() 14399 return combineSVEReductionInt(N, AArch64ISD::SMINV_PRED, DAG); in performIntrinsicCombine() 16526 case AArch64ISD::SMINV_PRED: in isLanes1toNKnownZero()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 257 SMINV_PRED, enumerator
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H A D | AArch64ISelLowering.cpp | 2022 MAKE_CASE(AArch64ISD::SMINV_PRED) in getTargetNodeName() 10973 return LowerReductionToSVE(AArch64ISD::SMINV_PRED, Op, DAG); in LowerVECREDUCE() 14399 return combineSVEReductionInt(N, AArch64ISD::SMINV_PRED, DAG); in performIntrinsicCombine() 16526 case AArch64ISD::SMINV_PRED: in isLanes1toNKnownZero()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 257 SMINV_PRED, enumerator
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H A D | AArch64ISelLowering.cpp | 2022 MAKE_CASE(AArch64ISD::SMINV_PRED) in getTargetNodeName() 10973 return LowerReductionToSVE(AArch64ISD::SMINV_PRED, Op, DAG); in LowerVECREDUCE() 14399 return combineSVEReductionInt(N, AArch64ISD::SMINV_PRED, DAG); in performIntrinsicCombine() 16526 case AArch64ISD::SMINV_PRED: in isLanes1toNKnownZero()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 257 SMINV_PRED, enumerator
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H A D | AArch64ISelLowering.cpp | 2022 MAKE_CASE(AArch64ISD::SMINV_PRED) in getTargetNodeName() 10973 return LowerReductionToSVE(AArch64ISD::SMINV_PRED, Op, DAG); in LowerVECREDUCE() 14399 return combineSVEReductionInt(N, AArch64ISD::SMINV_PRED, DAG); in performIntrinsicCombine() 16526 case AArch64ISD::SMINV_PRED: in isLanes1toNKnownZero()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 257 SMINV_PRED, enumerator
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H A D | AArch64ISelLowering.cpp | 2049 MAKE_CASE(AArch64ISD::SMINV_PRED) in getTargetNodeName() 11206 return LowerReductionToSVE(AArch64ISD::SMINV_PRED, Op, DAG); in LowerVECREDUCE() 14698 return combineSVEReductionInt(N, AArch64ISD::SMINV_PRED, DAG); in performIntrinsicCombine() 16826 case AArch64ISD::SMINV_PRED: in isLanes1toNKnownZero()
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